AD9832BRU-REEL Analog Devices Inc, AD9832BRU-REEL Datasheet - Page 14

• Manufacturer Part Number: AD9832BRU-REEL
• Description: IC,Numeric-Controlled Oscillator,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9832BRU-REEL

• Rohs Status: RoHS non-compliant
• Resolution (bits): 10 b
• Master Fclk: 25MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• For Use With: EVAL-AD9832EBZ - BOARD EVAL FOR AD9832

AD9832
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9832 has a serial interface, with 16 bits being loaded
during each write cycle. SCLK, SDATA, and FSYNC are used to
load the word into the AD9832.
When FSYNC is taken low, the AD9832 is informed that a word
is being written to the device. The first bit is read into the device
on the next SCLK falling edge with the remaining bits being read
into the device on the subsequent SCLK falling edges. FSYNC
frames the 16 bits; therefore, when 16 SCLK falling edges have
occurred, FSYNC should be taken high again. The SCLK can be
continuous, or alternatively, the SCLK can idle high or low between
write operations.
Table 5. Control Registers
Register
FREQ0 REG
FREQ1 REG
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
When writing to a frequency/phase register, the first four bits
identify whether a frequency or phase register is being written to,
the next four bits contain the address of the destination register,
while the 8 LSBs contain the data. Table 6 lists the addresses for
the phase/frequency registers, and Table 7 and Table 8 list the
data structure for each.
For an example on programming the AD9832, see the AN-621
application note, Programming the AD9832/AD9835, at
www.analog.com.
Size
32 bits
32 bits
12 bits
12 bits
12 bits
12 bits
Description
Frequency Register 0. This defines the
output frequency, when FSELECT = 0,
as a fraction of the MCLK frequency.
Frequency Register 1. This defines the
output frequency, when FSELECT = 1,
as a fraction of the MCLK frequency.
Phase Offset Register 0. When PSEL0 =
PSEL1 = 0, the contents of this register
are added to the output of the phase
accumulator.
Phase Offset Register 1. When PSEL0 = 1
and PSEL1 = 0, the contents of this
register are added to the output of the
phase accumulator.
Phase Offset Register 2. When PSEL0 = 0
and PSEL1 = 1, the contents of this
register are added to the output of the
phase accumulator.
Phase Offset Register 3. When PSEL0 =
PSEL1 = 1, the contents of this register
are added to the output of the phase
accumulator.
Rev. B | Page 14 of 24
Table 6. Addressing the Registers
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 7. 32-Bit Frequency Word
8 H MSBs
Table 8. 12-Bit Frequency Word
4 MSBs (The 4 MSBs of the
8-Bit Word Loaded = 0)
DIRECT DATA TRANSFER AND DEFERRED DATA
TRANSFER
Within the AD9832, 16-bit transfers are used when loading the
destination frequency/phase register. There are two modes for
loading a register, direct data transfer and a deferred data transfer.
With a deferred data transfer, the 8-bit word is loaded into the
defer register (8 LSBs or 8 MSBs). However, this data is not
loaded into the 16-bit data register; therefore, the destination
register is not updated. With a direct data transfer, the 8-bit word is
loaded into the appropriate defer register (8 LSBs or 8 MSBs).
Immediately following the loading of the defer register, the
contents of the complete defer register are loaded into the 16-bit
data register and the destination register is loaded on the next
MCLK rising edge. When a destination register is addressed, a
deferred transfer is needed first followed by a direct transfer.
When all 16 bits of the defer register contain relevant data, the
destination register can then be updated using 8-bit loading
rather than 16-bit loading, that is, direct data transfers can be
used. For example, after a new 16-bit word has been loaded to a
destination register, the defer register will also contain this
word. If the next write instruction is to the same destination
register, the user can use direct data transfers immediately.
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
16 MSBs
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
8 L MSBs
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8 H LSBs
8 LSBs
Destination Register
FREQ0 REG 8 L LSBs
FREQ0 REG 8 H LSBs
FREQ0 REG 8 L MSBs
FREQ0 REG 8 H MSBs
FREQ1 REG 8 L LSBs
FREQ1 REG 8 H LSBs
FREQ1 REG 8 L MSBs
FREQ1 REG 8 H MSBs
PHASE0 REG 8 LSBs
PHASE0 REG 8 MSBs
PHASE1 REG 8 LSBs
PHASE1 REG 8 MSBs
PHASE2 REG 8 LSBs
PHASE2 REG 8 MSBs
PHASE3 REG 8 LSBs
PHASE3 REG 8 MSBs
16 LSBs
8 L LSBs