AD9832BRU-REEL Analog Devices Inc, AD9832BRU-REEL Datasheet - Page 16

• Manufacturer Part Number: AD9832BRU-REEL
• Description: IC,Numeric-Controlled Oscillator,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9832BRU-REEL

• Rohs Status: RoHS non-compliant
• Resolution (bits): 10 b
• Master Fclk: 25MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• For Use With: EVAL-AD9832EBZ - BOARD EVAL FOR AD9832

AD9832
Table 11. Writing to the AD9832 Data Registers
D15
C3
1
Table 12. Setting SYNC and SELSRC
D15
1
1
Table 13. Power-Down, Resetting and Clearing the AD9832
D15
1
1
LATENCY
Associated with each operation is a latency. When inputs
FSELECT/PSEL change value, there is a pipeline delay before
control is transferred to the selected register; there is a pipeline
delay before the analog output is controlled by the selected
register. When times t
FSELECT have latencies of six MCLK cycles when SYNC = 0.
When SYNC = 1, the latency is increased to 8 MCLK cycles.
When times t
one MCLK cycle. Similarly, there is a latency associated with
each write operation. If a selected frequency/phase register is
loaded with a new word, there is a delay of 6 to 7 MCLK cycles
before the analog output will change (there is an uncertainty of
one MCLK cycle regarding the MCLK rising edge at which the
data is loaded into the destination register). When SYNC = 1,
the latency is 8 or 9 MCLK cycles.
X = don’t care.
X = don’t care.
X = don’t care.
D14
0
D14
1
D14
C2
11
and t
D13
SYNC
D13
SLEEP
D13
C1
11A
11
are not met, the latency can increase by
and t
D12
C0
11A
D12
SELSRC
D12
RESET
are met, PSEL0, PSEL1, and
D11
A3
D11
CLR
D11
X
1
D10
A2
D10
X
D10
X
1
1
D9
A1
Rev. B | Page 16 of 24
D9
X
D9
X
1
1
D8
A0
D8
X
D8
X
1
1
FLOWCHARTS
The flowchart in Figure 24 shows the operating routine for the
AD9832. When the AD9832 is powered up, the part should be
reset, which resets the phase accumulator to zero so that the
analog output is at midscale. To avoid spurious DAC outputs
while the AD9832 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
Taking CLR high sets SYNC and SELSRC to 0 so that the
FSELECT/PSELx pins are used to select the frequency/phase
registers, and the synchronization circuitry is bypassed. A write
operation is needed to the SYNC/SELSRC register to enable the
synchronization circuitry or to change control to the FSELECT/
PSEL bits. RESET does not reset the phase and frequency registers.
These registers will contain invalid data and, therefore, should
be set to a known value by the user. The RESET bit is then set to 0
to begin generating an output. A signal will appear at the DAC
output 6 MCLK cycles after RESET is set to 0.
The analog output is f
loaded into the selected frequency register. This signal is phase
shifted by the amount specified in the selected phase register
(2π/4096 × PHASEx REG, where PHASEx REG is the value
contained in the selected phase register).
Control of the frequency/phase registers can be interchanged
from the pins to the bits.
D7
MSB
D7
X
D7
X
1
1
D6
X
1
D6
X
D6
X
1
1
D5
X
1
D5
X
D5
X
1
MCLK
1
/2
D4
X
1
D4
X
32
D4
X
1
1
× FREG, where FREG is the value
D3
X
1
D3
X
D3
X
1
1
D2
X
1
D2
X
D2
X
1
1
D1
X
D1
X
1
D1
X
1
1
D0
LSB
D0
X
D0
X
1
1