AD9963BCPZRL Analog Devices Inc, AD9963BCPZRL Datasheet

no-image

AD9963BCPZRL

Manufacturer Part Number
AD9963BCPZRL
Description
Dual 16B, 200 MSPS D-A Converter
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9963BCPZRL

Package / Case
72-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
Dual 10-bit/12-bit, 100 MSPS ADC
Dual 10-bit/12-bit, 170 MSPS DAC
5 channels of analog auxiliary input/output
Low power, <425 mW at maximum sample rates
Supports full and half-duplex data interfaces
Small 72-lead LFCSP lead-free package
APPLICATIONS
Wireless infrastructure
Medical instrumentation
Portable instrumentation
GENERAL DESCRIPTION
The AD9961/AD9963 are pin-compatible, 10-/12-bit, low
power MxFE® converters that provide two ADC channels with
sample rates of 100 MSPS and two DAC channels with sample
rates to 170 MSPS. These converters are optimized for transmit
and receive signal paths of communication systems requiring low
power and low cost. The digital interfaces provide flexible
clocking options. The transmit is configurable for 1×, 2×, 4×,
and 8× interpolation. The receive path has a bypassable 2×
decimating low-pass filter.
The AD9961 and AD9963 have five auxiliary analog channels.
Three are inputs to a 12-bit ADC. Two of these inputs can be
configured as outputs by enabling 10-bit DACs. The other
two channels are dedicated outputs from two independent
12-bit DACs.
The high level of integrated functionality, small size, and low
power dissipation of the AD9961/AD9963 make them well-
suited for portable and low power applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
SNR = 67 dB, f
ACLR = 74 dBc
Picocell, femtocell basestations
Ultrasound AFE
Signal generators, signal analyzers
IN
= 30.1 MHz
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
PRODUCT HIGHLIGHTS
1.
2.
3.
TXIQ/TXnRX
TRXD[11:0]
TXD[11:0]
Low Power, Broadband MxFE
DLLFILT
TRXCLK
TXCLK
RESET
TRXIQ
CLKN
SCLK
CLKP
High Performance with Low Power Consumption.
The DACs operate on a single 1.8 V to 3.3 V supply.
Transmit path power consumption is <100 mW at 170
MSPS. Receive path power consumption is <350 mW at
100 MSPS from 1.8 V supply. Sleep and power-down
modes are provided for low power idle periods.
High Integration.
The dual transmit and dual receive data converters, five
channels of auxiliary data conversion and clock generation
offer complete solutions for many modem designs.
Flexible Digital Interface.
The interface mates seamlessly to most digital baseband
processors.
SDIO
CS
AD9961/AD9963
FUNCTIONAL BLOCK DIAGRAM
SERIAL
LOGIC
PORT
ASSEMBLER
DATA
DISTRIBUTION
REFERENCES
DLL AND
©2010 Analog Devices, Inc. All rights reserved.
AND BIAS
CLOCK
Figure 1.
AD9961/AD9963
TEMPERATURE
1/2/4/8
1/2/4/8
LPF
LPF
LPF
1/2
LPF
1/2
INTERNAL
SENSOR
ADC
DAC
DAC
AUX
AUX
AUX
VREGs
LDO
10-/12-Bit,
AUX
DAC
AUX
DAC
12-BIT
12-BIT
12-BIT
12-BIT
DAC
DAC
ADC
ADC
MUX
www.analog.com
AUXIN1
AUXIO2
AUXIO3
TXIP
TXIN
TXQP
TXQN
RXIP
RXIN
RXQP
RXQN
DAC12A
DAC12B

Related parts for AD9963BCPZRL

AD9963BCPZRL Summary of contents

Page 1

FEATURES Dual 10-bit/12-bit, 100 MSPS ADC SNR = 67 dB 30.1 MHz IN Dual 10-bit/12-bit, 170 MSPS DAC ACLR = 74 dBc 5 channels of analog auxiliary input/output Low power, <425 mW at maximum sample rates Supports full ...

Page 2

AD9961/AD9963 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations and Function ...

Page 3

SPECIFICATIONS RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, I MIN MAX interpolation, unless otherwise noted. Table 1. Tx Path Specifications Parameter TxDAC DC CHARACTERISTICS Resolution Differential Nonlinearity Gain ...

Page 4

AD9961/AD9963 RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, ADC sample rate = 100 MSPS. No MIN MAX decimation, unless otherwise noted. Table 2. Rx Path Specifications Parameter Rx ...

Page 5

RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, unless otherwise noted. MIN MAX Table 3. Auxiliary Converter Specifications Parameter AUXILIARY DAC12A/AUXDAC12B Resolution Differential Nonlinearity Gain Error Settling Time (±1%) ...

Page 6

AD9961/AD9963 f = 125 MHz 250 MHz, DAC sample rate = 125 MSPS, ADC sample rate = 62.5 MSPS, unless otherwise noted. CLK DLL Table 4. Power Consumption Specifications Parameter 1.8 V ONLY OPERATION (EXTERNAL 1.8 V) CLK33V ...

Page 7

Table 5. Digital Logic Level Specifications Parameter CMOS INPUT LOGIC LEVEL V Logic High IN V Logic High IN V Logic High IN V Logic Low IN V Logic Low IN V Logic Low IN CMOS OUTPUT LOGIC LEVEL V ...

Page 8

AD9961/AD9963 ABSOLUTE MAXIMUM RATINGS Table 6. With Parameter Respect to RX33V, AUX33V RXGND TXVDD TXGND DRVDD DGND CLK33V EPAD RX18V, RX18VF RXGND DVDD18V EPAD CLK18V, DLL18V EPAD RXGND, TXGND, DGND, EPAD TXIP, TXIN, TXQP, TXQN TXGND RXIP, RXIN, RXQP, RXQN ...

Page 9

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AUX33V AUXADCREF RXGND RXBIAS RX18VF RXGND LDO_EN NOTES 1. EXPOSED PAD MUST BE SOLDERED TO PCB CONNECT. Table 8. AD9961 Pin Function Descriptions Pin No. Mnemonic Description 1 AUX33V Analog Supply ...

Page 10

AD9961/AD9963 Pin No. Mnemonic Description 36 TRXCLK Qualifying Clock for the TRXD Bus. 37 TXCLK Qualifying Clock for the TXD Bus. It can be configured as either an input or output. 38 TXIQ/TXnRX Dual Function Pin. In half-duplex mode (TXnRX), ...

Page 11

AUX33V AUXADCREF RXGND RXBIAS RX18VF RXGND LDO_EN NOTES 1. EXPOSED PAD MUST BE SOLDERED TO PCB. Table 9. AD9963 Pin Function Descriptions Pin No. Mnemonic Description 1 AUX33V Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± ...

Page 12

AD9961/AD9963 Pin No. Mnemonic Description 54 DLLFILT DLL Filter Output. 55 CLK18V Output of CLK18V Voltage Regulator. 56,57 CLKN, CLKP Differential Input Clock. 58 CLK33V Input to CLK18V and DLL18V Voltage Regulators (1 3.3 V). If LDOs are ...

Page 13

TYPICAL PERFORMANCE CHARACTERISTICS 2mA 1mA (MHz) OUT Figure 4. Second Harmonic Distortion vs. f OUT f = 125 MHz, 1×, Digital ...

Page 14

AD9961/AD9963 100 0dBFS 75 –3dBFS 70 65 –6dBFS (MHz) OUT Figure 10. Second Harmonic Distortion vs 125 MHz, 1×, Full-Scale Current = 2 mA, TXVDD = 3.3 ...

Page 15

TEMPER ATURE (°C) Figure 16. Typical Die Temperature Readback Error vs. Ambient Temperature REF ...

Page 16

AD9961/AD9963 1.2 1.0 0.8 INL 0.6 DNL 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 0 512 1024 1536 2048 2560 CODE Figure 22. Rx Path ADC, INL and DNL 155 IDAC, 125MHz, 4mA, 0dB 153 151 IDAC, 125MHz, ...

Page 17

MIN PIPE SFDR (dBFS) MID PIPE SFDR (dBFS) MAX PIPE SFDR (dBFS) 80 MIN PIPE SNR (dBFS) MID PIPE SNR (dBFS) 75 MAX PIPE SNR (dBFS ...

Page 18

AD9961/AD9963 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) ...

Page 19

THEORY OF OPERATION The AD9961/AD9963 are targeted to cover the mixed-signal front-end needs of multiple wireless communications systems. They feature a receive path that consists of dual 10-/12-bit receive ADCs and a transmit path that consists of dual 10-/12-bit transmit ...

Page 20

AD9961/AD9963 SERIAL CONTROL PORT The AD9961/AD9963 serial control ports are a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9961/AD9963 serial control ports are compatible with most synchronous transfer formats, including ...

Page 21

When LSB first is set by Register 0x00, Bit 2 and Register 0x00, Bit 6, it takes effect immediately. In multibyte transfers, subsequent bytes reflect any changes in the serial port configuration. To avoid problems reconfiguring the serial port operation, ...

Page 22

AD9961/AD9963 SCLK SDIO CS SCLK DON’T CARE SDIO DON’T CARE 16-BIT INSTRUCTION HEADER Figure 37. Serial Control Port Access—LSB First, 16-Bit Instruction, Two Bytes Data SCLK SDIO Table ...

Page 23

CONFIGURATION REGISTERS Table 14. Configuration Register Map Addr Default Bit 7 Bit 6 0x00 0x18 SDIO LSB First 0x05 0x00 0x0F 0x00 0x10 0x00 Unused 0x30 0x3F Unused 0x31 0xA7 TX_SDR TXCKO_INV 0x32 0xA7 RX_SDR Unused 0x33 Varies Unused FIFO_INIT ...

Page 24

AD9961/AD9963 Addr Default Bit 7 Bit 6 0x71 0x00 ADCCLKSEL DACCLKSEL 0x72 0x01 DLL_Locked 0x75 0x00 0x77 0x00 CONV_TIME[1:0] 0x78 Varies 0x79 Varies 0x7A 0x00 AUXADC_EN AUXADC_RESB 0x7B 0x00 TMPSNS_EN 0x7D 0x00 Unused 0x7E 0x00 Unused RXTrim_EN 0x7F 0x00 0x80 ...

Page 25

Register Register Name Address Bit( Data Interface 0x31 Data Interface 0x32 7 6 5:4 Parameter Function SRRC_BP 1: bypass 2× SRRC interpolation filter (SRRC). The filter chain is ...

Page 26

AD9961/AD9963 Register Register Name Address Bit( FIFO Alignment 0x33 2:0 FIFO Status 0x34 7:0 Tx Scale P 0x35 7:5 4:0 Tx Scale 0 0x36 7:5 4:0 Parameter Function 11: RXCLK is ...

Page 27

Register Register Name Address Bit(s) Tx Scale 1 0x37 7:5 4:0 Rx Scale 0x38 7:5 4:0 Clock Doubler 0x39 7 Config 6 5 Clock Doubler 0x3A 7:4 Config Clock Doubler 0x3B ...

Page 28

AD9961/AD9963 Register Register Name Address Bit(s) Rx Data Interface 0x3F DAC12 Config 0x40 3 DAC12A MSBs 0x41 7:0 DAC12A LSBs 0x42 7:4 3:0 DAC12B MSBs 0x43 ...

Page 29

Register Register Name Address Bit(s) 1:0 DAC10BMSBs 0x46 7:0 DAC10BLSBs 0x47 7:2 1:0 DAC10A Config 0x48 7 6:5 4:2 1:0 DAC10A MSBs 0x49 7:0 DAC10A LSBs 0x4A 7:2 1:0 TX BIST Control 0x50 7 ...

Page 30

AD9961/AD9963 Register Register Name Address Bit( TXI Check MSB 0x52 7:0 TXI Check LSB 0x53 7:0 TXQ Check MSB 0x54 7:0 TXQ Check LSB 0x55 7:0 Version 0x5C 7:0 Power Down 0 0x60 ...

Page 31

Register Register Name Address Bit(s) 3:2 1:0 Clock Mode 0x66 1:0 I DAC Gain Ctrl 0 0x68 7:6 5:0 I DAC Gain Ctrl 1 0x69 7:6 5:0 I DAC Gain Ctrl 2 0x6A 7:6 ...

Page 32

AD9961/AD9963 Register Register Name Address Bit(s) DLL Control 0 0x71 3:0 DLL Control 1 0x72 7 6:5 4:0 DLL Control 2 0x75 7:4 3 2:0 Aux ADC Config 0x77 7:6 and Conversion Start 5:3 2:0 Parameter ...

Page 33

Register Register Name Address Bit(s) Aux ADC MSBs 0x78 7:0 Aux ADC LSBs 0x79 7:4 3 2:0 Aux ADC CTRL 0 0x7A 7 6 5:3 2:0 Aux ADC CTRL 1 0x7B 7 6:5 4:2 1:0 ADC Full-Scale Adj 0x7D 7:5 ...

Page 34

AD9961/AD9963 Register Register Name Address Bit(s) Rx ADC Trim Ctrl 0x7E 3:1 0 IGAIN CAL MSBs 0x7F 7:0 IGAIN CAL LSBS 0x80 7:3 2:1 0 IGAIN CAL MSBs 0x81 7:0 IGAIN CAL LSBs 0x82 7:3 2:1 ...

Page 35

RECEIVE PATH Rx Path General Description The AD9961/AD9963 Rx paths consist of dual, differential input, 100 MSPS ADCs followed by an optional 2× decimation filter. The Rx path also has digital offset and gain adjustments. I OFFSET RXIP I ADC ...

Page 36

AD9961/AD9963 200Ω 200Ω +VIN V ADA4937 CC 33Ω 1kΩ VOCM 0.1µF 1kΩ 33Ω –VIN 200Ω 200Ω Figure 41. Differential Input Configuration, AC-Coupled The output common-mode voltage of the match the common-mode voltage required by the ADC by connecting the RXCML ...

Page 37

NORMALIZED FREQUENCY (Relative to f Figure 46. Pass-Band Response of the Rx Path Decimation Filter The filter coefficients of the 2× decimation low-pass are shown in Table 16. Table 16. Lower ...

Page 38

AD9961/AD9963 TRANSMIT PATH Tx Path General Description The transmit section consists of two complete paths of interpolation filters stages, each followed by a high speed current output DAC. A data assembler receives interleaved data from one of two digital interface ...

Page 39

Interpolation Filter Coefficients The interpolation filters, INT0 and INT1, are half-band filters implemented with a symmetric set of coefficients. Every other coefficient (even coefficients) except the center coefficient is zero. The coefficient values for the three interpolation filters are listed ...

Page 40

AD9961/AD9963 13 TXD[11:0] INPUT TXIQ LATCH TXCLK_MD 1 0 Reg 0x31[0] TXCKI_INV 1 0 Reg 0x31[3] EN TXCLK TXCKO_INV Reg 0x31[6] Figure 52. Transmit Path Data Flow and Clock Generation In Full Duplex Mode The signal on ...

Page 41

Transmit Path Gain Adjustment Adjusting the output signal level is implemented by scaling the full-scale output current of the transmit DAC. There are four separate programmable parameters that can be used to adjust the full-scale output of the DACs; the ...

Page 42

AD9961/AD9963 –2 –4 –6 – GAIN1 Figure 56. Typical DAC Full-Scale Current vs. GAIN1 Code 2.06 2.04 2.02 2.00 1.98 1.96 1. GAIN2 Figure ...

Page 43

The circuit shown in Figure 60 shows a typical output circuit configuration that provides a non zero bias voltage at the TXCML pin. Resistance values of 499 Ω for R R produces p-p differential output voltage swing ...

Page 44

AD9961/AD9963 R B AD9961/AD9963 R S TXIP 65 REFIO 63 C TXGND TXIN Figure 62. Single-Supply Differential Buffer Single-Ended Buffered Output Using an Op Amp An op amp such as the ADA4899-1 can be ...

Page 45

DEVICE CLOCKING CLOCK DISTRIBUTION The clock distribution diagram shown in Figure 65 gives an overview of the clocking options for each of the data converters. The receive path ADCs and the transmit path DACs can be clocked directly from the ...

Page 46

AD9961/AD9963 DRIVING THE CLOCK INPUT For optimum performance, the AD9961/AD9963 clock inputs (CLKP and CLKN) should be clocked with a low jitter, fast rise time differential signal. This signal should be ac-coupled to the CLKP and CLKN pins via a ...

Page 47

The DLL is composed of a ring oscillator made from a programmable delay line. The ring oscillator output signal is labeled as MCLK. The MCLK signal is set to oscillate at a frequency M times greater than the REFCLK signal. ...

Page 48

AD9961/AD9963 DIGITAL INTERFACES The AD9961/AD9963 have two parallel interface ports, the Tx port and the TRx port. The operation of the ports depends on whether the device is configured for full-duplex or half- duplex mode. In full-duplex mode, the TRx ...

Page 49

TRXCLK TRXIQ TRXD[11:0] I0 Figure 75. Rx Timing, I ADC Only, Bus Rate Clock Mode t OD2 TRXCLK TRXIQ TRXD[11:0] Q0 Figure 76. Rx Timing, Q ADC Only, Bus Rate Clock Mode t OD2 TRXCLK TRXIQ TRXD[11:0] I0 Figure ...

Page 50

AD9961/AD9963 The Tx port has an optional double data rate (DDR) clock mode. In DDR mode, the transmit data is latched on both the rising and falling edges of TXCLK. The polarity of the edge identifies to which channel the ...

Page 51

Table 26 shows the operating modes vs. serial port configuration bits. Table 26. TRx Bus Operation via Serial Port TRXD Bus TXEN RXEN Direction 0 0 High Table 27 shows the ...

Page 52

AD9961/AD9963 AUXILIARY CONVERTERS The AD9961/AD9963 have two fast settling servo DACs, along with an analog input and two analog I/O pins. All of the auxiliary converters run off a dedicated supply pin. The input and output compliance ranges depend on ...

Page 53

Digital Output Coding The digital output coding is straight binary. The ideal transfer characteristic for the auxiliary ADC is shown in Figure 86. 111 ... 111 111 ... 110 111 ... 101 000 ... 010 000 ... 001 000 ... ...

Page 54

AD9961/AD9963 The curves in Figure 89 represent four of the possible DAC transfer functions with the full-scale voltage of 3.0 V and spans of 0.5 V, 1.0 V, 1.5 V, and 2.0 V. The curves in Figure 90 represent four ...

Page 55

POWER SUPPLIES The AD9961/AD9963 power distributions are shown in Figure 93. The functional blocks labeled Rx ANLG, Rx ADCs, SPI and digital core, clocking, and DLL operate from 1.8 V supplies. The functional blocks labeled Tx DACs, AUX DACs and ...

Page 56

AD9961/AD9963 80 RX18V RX18VF (MHz) ADC Figure 96. I and I vs Both ADCs Enabled RX18V RX18VF ADC 4mA ...

Page 57

DAC Figure 102 1×, 2×, 4×, 8× (Tx only) DVDD18 DAC 3.3V 2.5V 15 1.8V ...

Page 58

... Model Temperature Range AD9961BCPZ −40°C to +85°C AD9961BCPZRL −40°C to +85°C AD9963BCPZ −40°C to +85°C AD9963BCPZRL −40°C to +85°C AD9961-EBZ −40°C to +85°C AD9963-EBZ −40°C to +85°C HSC-DAC-EVALCZ −40°C to +85° RoHS Compliant Part. ...

Page 59

NOTES Rev Page AD9961/AD9963 ...

Page 60

AD9961/AD9963 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08801-0-7/10(0) Rev Page ...

Related keywords