ADCLK846/PCBZ Analog Devices Inc, ADCLK846/PCBZ Datasheet

no-image

ADCLK846/PCBZ

Manufacturer Part Number
ADCLK846/PCBZ
Description
Evaluation Kit 1.8V 6:VDS/12 CMOS Cl
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADCLK846/PCBZ

Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Main Purpose
Timing, Clock Buffer / Driver / Receiver / Translator
Utilized Ic / Part
ADCLK846
Primary Attributes
6 LVDS/12 CMOS Outputs
Secondary Attributes
CMOS, LVDS Outputs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Embedded
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
FEATURES
Selectable LVDS/CMOS outputs
Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs
<16 mW per channel (100 MHz operation)
54 fs integrated jitter (12 kHz to 20 MHz)
100 fs additive broadband jitter
2.0 ns propagation delay (LVDS)
135 ps output rise/fall (LVDS)
65 ps output-to-output skew (LVDS)
Sleep mode
Pin-programmable control
1.8 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout
buffer optimized for low jitter and low power operation. Possible
configurations range from 6 LVDS to 12 CMOS outputs,
including combinations of LVDS and CMOS outputs. Two
control lines are used to determine whether fixed blocks of
outputs are LVDS or CMOS outputs.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Low Power Clock Fanout Buffer
1.8 V, 6 LVDS/12 CMOS Outputs
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The clock input accepts various types of single-ended and
differential logic levels including LVPECL, LVDS, HSTL, CML,
and CMOS.
Table 8 provides interface options for each type of connection.
The SLEEP pin enables a sleep mode to power down the device.
This device is available in a 24-pin LFCSP package. It is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
CTRL_A
CTRL_B
SLEEP
V
CLK
CLK
REF
FUNCTIONAL BLOCK DIAGRAM
ADCLK846
©2009–2010 Analog Devices, Inc. All rights reserved.
LVDS/CMOS
LVDS/CMOS
Figure 1.
ADCLK846
OUT0 (OUT0A)
OUT0 (OUT0B)
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
OUT3 (OUT3A)
OUT3 (OUT3B)
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
www.analog.com

Related parts for ADCLK846/PCBZ

ADCLK846/PCBZ Summary of contents

Page 1

FEATURES Selectable LVDS/CMOS outputs LVDS (1.2 GHz CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation integrated jitter (12 kHz to 20 MHz) 100 fs additive broadband jitter 2.0 ns propagation ...

Page 2

ADCLK846 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Characteristics ............................................................. 3 Timing Characteristics ................................................................ 4 Clock Characteristics ................................................................... 5 Logic and ...

Page 3

SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical values are given for V = 1.8 V and 1.8 V ± 5% and T = −40°C to +85°C variations, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted. ...

Page 4

ADCLK846 TIMING CHARACTERISTICS Table 2. Parameter LVDS OUTPUTS Output Rise/Fall Time Propagation Delay, CLK-to-LVDS Output Temperature Coefficient 1 Output Skew All LVDS Outputs on the Same Part All LVDS Outputs Across Multiple Parts Additive Time Jitter Integrated Random Jitter Broadband ...

Page 5

CLOCK CHARACTERISTICS Table 3. Clock Output Phase Noise Parameter CLK-TO-LVDS ABSOLUTE PHASE NOISE 1000 MHz CLK-TO-CMOS ABSOLUTE PHASE NOISE 200 MHz LOGIC AND POWER CHARACTERISTICS Table 4. Control Pin Characteristics Parameter CONTROL PINS 1 (CTRL_A, CTRL_B, SLEEP) Logic 1 Voltage ...

Page 6

ADCLK846 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage V to GND S Inputs CLK and CLK CMOS Inputs Outputs Maximum Voltage Voltage Reference Voltage (V ) REF Operating Temperature Range Ambient Junction Storage Temperature Range Stresses above those listed ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Descriptions Pin No. Mnemonic 1 V REF 2 CLK 3 CLK 4, 10, 13, 16, 19 CTRL_A 6 CTRL_B 7 SLEEP 8 OUT5 (OUT5B) 9 OUT5 (OUT5A) ...

Page 8

ADCLK846 TYPICAL PERFORMANCE CHARACTERISTICS 25°C, unless otherwise noted CH2 100mV M 200ps 10.0GS/s Figure 3. LVDS Output Waveform at 1200 MHz 2.3 2.2 2.1 2.0 1.9 1.8 1.7 0.1 0.3 0.5 ...

Page 9

INPUT FREQUENCY (MHz) Figure 9. LVDS Differential Output Swing vs. Input Frequency 150 125 100 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) Figure 10. LVDS Current vs. ...

Page 10

ADCLK846 1 CH1 300mV 1.25ns/DIV Figure 15. CMOS Output Waveform at 200 MHz Load 1.9 1.8 25°C 1.7 1.6 85°C 1.5 1.4 1.3 1.2 1.1 50 100 150 FREQUENCY (MHz) Figure 16. CMOS Output Swing vs. Frequency and ...

Page 11

FUNCTIONAL DESCRIPTION The ADCLK846 clock input is distributed to all output channels. Each channel bank is pin programmable for either LVDS or CMOS levels. This allows the selection of multiple logic configurations ranging from 6 LVDS to 12 CMOS outputs, ...

Page 12

... PCB with adequate capacitance (>10 μF) and bypassing all power pins with adequate capacitance (0.1 μF) as close to the part as possible. The layout of the ADCLK846 evaluation board (ADCLK846/PCBZ) provides a good layout example. Exposed Metal Paddle The exposed metal paddle on the ADCLK846 package is an electrical connection, as well as a thermal enhancement ...

Page 13

APPLICATIONS INFORMATION USING THE ADCLK846 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer, ...

Page 14

ADCLK846 Termination at the far end of the PCB trace is a second option. The CMOS outputs of the ADCLK846 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown ...

Page 15

... INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADCLK846BCPZ −40°C to +85°C ADCLK846BCPZ-REEL7 −40°C to +85°C ADCLK846/PCBZ RoHS Compliant Part. 0.60 MAX 4.00 BSC SQ 0.60 MAX 19 18 0.50 BSC TOP 3.75 EXPOSED VIEW BSC SQ (BO TT OMVIEW) 0 ...

Page 16

ADCLK846 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07226-0-5/10(B) Rev Page ...

Related keywords