ADF4001BCPZ-RL Analog Devices Inc, ADF4001BCPZ-RL Datasheet

Clock Generation PLL

ADF4001BCPZ-RL

Manufacturer Part Number
ADF4001BCPZ-RL
Description
Clock Generation PLL
Manufacturer
Analog Devices Inc
Type
Clock Generator (RF)r
Datasheet

Specifications of ADF4001BCPZ-RL

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
200MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-LFCSP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4001EBZ2 - BOARD EVAL FOR ADF4001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
a
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
Tuning Voltage in 5 V Systems
ADF4112/ADF4113
RF
RF
REF
DATA
CLK
IN
IN
LE
IN
A
B
INPUT REGISTER
SD
24-BIT
OUT
AV
ADF4001
DD
DV
CE
22
P
DD
) Allows Extended
R COUNTER
R COUNTER
N COUNTER
N COUNTER
FUNCTION
FUNCTIONAL BLOCK DIAGRAM
14-BIT
LATCH
LATCH
LATCH
13-BIT
14
13
AGND
DGND
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REF
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an exter-
nal loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
V
LOCK DETECT
P
200 MHz Clock Generator PLL
FREQUENCY
DETECTOR
PHASE
SD
CPGND
OUT
AV
DD
CPI3 CPI2
CURRENT
SETTING 1
© 2003 Analog Devices, Inc. All rights reserved.
M3
MUX
M2
REFERENCE
CPI1 CPI6 CPI5
CHARGE
PUMP
M1
CURRENT
SETTING 2
HIGH Z
R
SET
CPI4
ADF4001
CP
MUXOUT
www.analog.com
IN

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ADF4001BCPZ-RL Summary of contents

Page 1

FEATURES 200 MHz Bandwidth 2 5.5 V Power Supply Separate Charge Pump Supply (V Tuning Voltage Systems Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect ...

Page 2

ADF4001–SPECIFICATIONS CPGND = 4 SET A MIN Parameter RF CHARACTERISTICS ( Input Frequency RF Input Sensitivity RF CHARACTERISTICS ( Input Frequency REF CHARACTERISTICS IN REF ...

Page 3

TIMING CHARACTERISTICS unless otherwise noted; dBm referred to 50 SET A MIN MAX Limit at T MIN Parameter (B Version ...

Page 4

ADF4001 TSSOP R 1 SET CP 2 ADF4001 CPGND 3 AGND 4 TOP VIEW (Not to Scale REF 8 IN TSSOP LFCSP Pin No. Pin No. Mnemonic 1 19 ...

Page 5

–25 –30 – 100 150 FREQUENCY – MHz TPC 1. Input Sensitivity 3.3 V, 100 –5 –10 –15 –20 –25 –30 ...

Page 6

ADF4001 CIRCUIT DESCRIPTION Reference Input Section The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ...

Page 7

ANALOG LOCK DETECT DIGITAL LOCK DETECT MUX R COUNTER OUTPUT N COUNTER OUTPUT SDOUT Figure 6. MUXOUT Circuit Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect ...

Page 8

ADF4001 ANTI- TEST BACKLASH RESERVED MODE WIDTH BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 LDP T2 T1 ABP2 X = DON’T CARE ABP2 TEST MODE BITS SHOULD BE SET TO 00 FOR ...

Page 9

RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 X G1 N13 N12 N11 N10 X N13 N12 ...

Page 10

ADF4001 CURRENT CURRENT RESERVED SETTING SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 X X PD2 CPI6 CPI5 CPI4 CPI3 X = DON’T CARE TC4 TC3 ...

Page 11

CURRENT CURRENT RESERVED SETTING SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 PD2 CPI6 CPI5 CPI4 CPI3 DON’T CARE TC4 ...

Page 12

ADF4001 FUNCTION LATCH With C2, C1 set the on-chip function latch will be pro- grammed. Table V shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. When ...

Page 13

INITIALIZATION LATCH When C2 the initialization latch is programmed. This is essentially the same as the function latch (programmed when C2 0). However, when the initialization latch is programmed, there is an additional ...

Page 14

ADF4001 COHERENT CLOCK GENERATION When testing A/D converters often advantageous to use a coherent test system, that is, a system that ensures a specific relationship between the A/D converter input signal and the A/D converter sample rate. Thus, ...

Page 15

INTERFACING ® The ADF4001 family has a simple SPI face for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register ...

Page 16

ADF4001 16-Lead Thin Shrink Small Outline Package [TSSOP] 0.15 0.05 PIN 1 INDICATOR 12 MAX 1.00 0.90 0.80 SEATING PLANE Revision History Location 10/03—Data Sheet changed from REV REV. A. Changes to SPECIFICATIONS . . . . . ...

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