ADF4360-9BCPZ Analog Devices Inc, ADF4360-9BCPZ Datasheet
ADF4360-9BCPZ
Specifications of ADF4360-9BCPZ
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ADF4360-9BCPZ Summary of contents
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... GENERAL DESCRIPTION The ADF4360 integrated integer-N synthesizer and voltage-controlled oscillator (VCO). External inductors set the ADF4360-9 center frequency. This allows a VCO frequency range of between 65 MHz and 400 MHz. An additional divider stage allows division of the VCO signal. The CMOS level output is equivalent to the VCO signal divided by the integer value between 2 and 31 ...
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... ADF4360-9 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description......................................................................... 10 Reference Input Section............................................................. 10 N Counter.................................................................................... 10 R Counter .................................................................................... 10 PFD and Charge Pump.............................................................. 10 Lock Detect ...
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... Inductance Value section for other frequency values 1.2 Ratio f MAX 2 MHz/V typ L1 270 nH; see the Choosing the Correct Inductance Value section for other sensitivity values 400 μs typ To within final frequency Rev Page ADF4360 4.7 kΩ SET ≤ 2 ≤ 500 μ mA; depending on L1 and L2; see the /f ...
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... VCO and subtracting 20logN (where N is the N divider value) and 10logf 12 The jitter is measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REF synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. f noted ...
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... DB22 DB2 (CONTROL BIT C2) Figure 2. Timing Diagram Rev Page ADF4360 unless otherwise noted. A MIN MAX Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width ...
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... ADF4360-9 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND VCO VCO DD Digital Input/Output Voltage to GND Analog Input/Output Voltage to GND REF to GND IN Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θ Thermal Impedance JA Paddle Soldered Paddle Not Soldered ...
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... TUNE output voltage external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and L2 need to be the same value. A 470 Ω ...
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... ADF4360-9 TYPICAL PERFORMANCE CHARACTERISTICS –20 –40 –60 –80 –100 –120 –140 –160 1k 10k 100k FREQUENCY (Hz) Figure 4. Open-Loop VCO Phase Noise at 218 MHz, L1 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 100 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 5. VCO Phase Noise, 360 MHz, 1 MHz PFD, 40 kHz Loop Bandwidth, RMS Jitter = 1.4 ps – ...
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... Figure 13. DIVOUT 90 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected, 1 CH1 1M 10M Figure 14. DIVOUT 36 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected CH1 20mV CH1 Rev Page ADF4360-9 C1 FREQUENCY: 90MHz C1 + DUTY: 28.98% C1 PEAK TO PEAK: 1.55V 500mV M 2.00ns A CH1 Duty Cycle = ~25% C1 FREQUENCY: 36.01MHz C1 + DUTY: 13.13% C1 PEAK TO PEAK 1.28V 500mV M 5 ...
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... It stays set high until a phase error of > detected on any subsequent PD cycle. INPUT SHIFT REGISTER The digital section of the ADF4360 family includes a 24-bit input shift register, a 14-bit R counter, and an 18-bit N counter, comprising a 5-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK ...
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... Test Modes VCO The VCO core in the ADF4360 family uses eight overlapping bands, as shown in Figure 18, to allow a wide frequency range to be covered without a large VCO sensitivity (K poor phase noise and spurious performance. The correct band is chosen automatically by the band select logic at power-up or whenever the N counter latch is updated ...
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... BUFFER Figure 19. RF Output Stage DIVOUT STAGE The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of DIVOUT is controlled by D3, D2, and D1 in the control latch. The full truth table is shown in Figure 23. Figure 20 shows the DIVOUT section in block diagram form ...
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... LATCH STRUCTURE Figure 22 shows the three on-chip latches for the ADF4360-9. The two LSBs decide which latch is programmed. CURRENT SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 RSV RSV PD2 PD1 CPI6 CPI5 CPI4 DB23 DB22 DB21 DB20 DB19 ...
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... ADF4360-9 CURRENT SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI6 CPI5 CPI3 CPI2 PL2 PIN PD2 PD1 MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN ...
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... Figure 24. N Counter Latch Rev Page ADF4360-9 CONTROL 5-BIT DIVOUT DB7 DB6 DB5 DB4 DB3 DB2 DB1 B1 RSV ( OUTPUT DIVIDE RATIO ............ 0 0 NOT ALLOWED ............ 0 1 NOT ALLOWED ............ ...
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... ADF4360-9 BAND BACKLASH SELECT CLOCK DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV RSV BSC2 BSC1 TMB LDP ABP2 TEST MODE BIT SHOULD BE SET TO 0 FOR NORMAL THESE BITS ARE OPERATION. NOT USED BY THE DEVICE AND ARE DON'T CARE BITS ...
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... VCO may not oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band, and the ADF4360-9 may not achieve lock. If the recommended interval is inserted, and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency ...
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... The on-chip multiplexer is controlled by D3, D2, and D1 (see the truth table in Figure 23). Counter Reset DB4 is the counter reset bit for the ADF4360 family. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0. Core Power Level PC1 and PC2 set the power level in the VCO core ...
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... Overall Divide Range The overall VCO feedback divide range is defined Gain DB21 of the N counter latch in the ADF4360 family is the charge pump gain bit. When it is programmed to 1, Current Setting 2 is used. When programmed to 0, Current Setting 1 is used. This bit can also be programmed through DB10 of the control latch ...
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... A/2 mode is selected. Therefore programmed to 2, giving an overall divide value of 4. The that requires an encode clock jitter less. The ADF4360-9 takes a 10 MHz TCXO frequency and divides this to 1 MHz; therefore programmed and N = 320 is programmed to achieve a VCO frequency of 320 MHz ...
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... GSM TEST CLOCK Figure 30 shows the ADF4360-9 used to generate three different frequencies at DIVOUT. The frequencies required are 45 MHz, 80 MHz, and 95 MHz. This is achieved by generating 360 MHz, 320 MHz, and 380 MHz and programming the correct A divider ratio. Because a 50% duty cycle is required, the A/2 DIVOUT mode is selected ...
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... The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4360 family needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. After the third byte is written, the LE input should be brought high to complete the transfer ...
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... OUTPUT MATCHING There are a number of ways to match the VCO output of the ADF4360-9 for optimum operation; the most basic is to use a 51 Ω resistor bypass capacitor of 100 pF is connected VCO in series, as shown in Figure 33. Because the resistor is not frequency dependent, this provides a good broadband match. ...
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... Model Temperature Range 1 ADF4360-9BCPZ −40°C to +85°C 1 ADF4360-9BCPZRL −40°C to +85°C 1 ADF4360-9BCPZRL7 −40°C to +85°C 1 EVAL-ADF4360-9EBZ1 RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 4.00 BSC SQ ...