ADF4360-9BCPZ Analog Devices Inc, ADF4360-9BCPZ Datasheet - Page 7

• Manufacturer Part Number: ADF4360-9BCPZ
• Description: Synthesizer And VCO
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-9BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 5mA
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 250MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: LFCSP EP
• Output Frequency Range: 1.1 to 400MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3, 8, 11, 22
4
5
6
7
9
10
12
13
14
15
16
17
18
19
20
21
23
24
AGND
Mnemonic
CPGND
AV
RF
RF
V
V
L1
L2
C
R
C
DGND
REF
CLK
DATA
LE
DIVOUT
DV
LD
CP
VCO
TUNE
C
SET
N
OUT
OUT
DD
DD
IN
A
B
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler and VCO.
Description
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
description of the various output stages.
VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output
Matching section for a description of the various output stages.
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the R
For example, R
Internal Compensation Node. This pin must be decoupled to V
Digital Ground.
Reference Input. This is a CMOS input with a nominal threshold of V
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A.
Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DV
Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
Charge Pump Output. When enabled, this provides ±I
internal VCO.
I
CPmax
= 11.75/R
SET
= 4.7 kΩ and I
SET
RF
RF
CPGND
AGND
AV
OUT
OUT
V
VCO
DD
A
B
Figure 3. Pin Configuration
1
2
3
4
5
6
CPmax
Rev. A | Page 7 of 24
ADF4360-9
(Not to Scale)
= 2.5 mA.
TOP VIEW
PIN 1
INDICATOR
DD
must have the same value as AV
VCO
18 DATA
17 CLK
16 REF
15 DGND
14 C
13 R
SET
DD
must have the same value as AV
pin is 0.6 V. The relationship between I
N
SET
CP
must have the same value as DV
IN
to the external loop filter, which in turn drives the
VCO
with a 10 μF capacitor.
DD
/2 and a dc equivalent input resistance of
DD
.
DD
DD
.
.
CP
ADF4360-9
and R
SET
is