ADF4360-9BCPZ Analog Devices Inc, ADF4360-9BCPZ Datasheet - Page 17

• Manufacturer Part Number: ADF4360-9BCPZ
• Description: Synthesizer And VCO
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-9BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 5mA
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 250MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: LFCSP EP
• Output Frequency Range: 1.1 to 400MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-9 after
power-up is as follows:
1.
2.
3.
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AV
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-9 during initial power-up to settle.
Table 6. C
C
10 μF
440 nF
N
Value
R Counter Latch
Control Latch
N Counter Latch
N
Capacitance vs. Interval and Phase Noise
Recommended Interval Between
Control Latch and N Counter Latch
≥15 ms
≥600 μs
POWER-UP
DATA
CLK
LE
DD
, DV
DD
LATCH DATA
R COUNTER
, and V
VCO
pins. On
L1 and L2 = 18.0 nH
−100 dBc/Hz
−99 dBc/Hz
Figure 26. Power-Up Timing
Rev. A | Page 17 of 24
LATCH DATA
CONTROL
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-9 may not achieve lock. If the
recommended interval is inserted, and the N counter latch is
programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the C
reduce the close-in noise of the ADF4360-9 VCO. The
recommended value of this capacitor is 10 μF. Using this
value requires an interval of ≥15 ms between the latching in
of the control latch bits and latching in of the N counter latch
bits. If a shorter delay is required, the capacitor can be reduced.
A slight phase noise penalty is incurred by this change, which is
further explained in Table 6.
Open-Loop Phase Noise @ 10 kHz Offset
L1 and L2 = 110.0 nH
−97 dBc/Hz
−96 dBc/Hz
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
REQUIRED INTERVAL
N
pin (Pin 14). This capacitor is used to
LATCH DATA
N COUNTER
L1 and L2 = 560.0 nH
−99 dBc/Hz
−98 dBc/Hz
ADF4360-9