ADL5371ACPZ-R7 Analog Devices Inc, ADL5371ACPZ-R7 Datasheet - Page 11

• Manufacturer Part Number: ADL5371ACPZ-R7
• Description: IC,RF Modulator,LLCC,24PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADL5371ACPZ-R7

• Design Resources: Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
• Function: Modulator
• Lo Frequency: 500MHz ~ 1.5GHz
• Rf Frequency: 500MHz ~ 1.5GHz
• P1db: 14.4dBm
• Noise Floor: -158.6dBm/Hz
• Output Power: 7.6dBm
• Current - Supply: 200mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Test Frequency: 900MHz
• Package / Case: 24-VFQFN, 24-CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADL5371ACPZ-R7TR

BASIC CONNECTIONS
Figure 23 shows the basic connections for the ADL5371.
POWER SUPPLY AND GROUNDING
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Application Note
thermal and electrical grounding of the LFCSP in detail.
COM1
COM1
VPS1
VPS1
VPS1
VPS1
C12
0.1µF
QBBP
1
2
3
4
5
6
GND
Figure 23. Basic Connections for the ADL5371
100pF
CLOP
LO
EXPOSED PADDLE
QBBN
F-MOD
Z1
CLON
100pF
IBBN
IBBP
18
17
16
15
14
13
AN-772
COUT
100pF
VPS5
VPS4
VPS3
VPS2
VPS2
VOUT
0.1µF
C13
discusses the
C16
0.1µF
C15
0.1µF
C14
0.1µF
OPEN
C11
VPOS
VOUT
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BASEBAND INPUTS
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs range
from 400 mV to 600 mV. This results in a reduction in the
usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5371 input range and on the top end by the output compliance
range on most DACs from Analog Devices.
LO INPUT
A single-ended LO signal should be applied to the LOIP pin
through an ac coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.
The nominal LO drive of 0 dBm can be increased to up to 7 dBm
to realize an improvement in the noise performance of the
modulator (see Figure 33). This improvement is tempered by
degradation in the sideband suppression performance (see
Figure 19) and, therefore, should be used judiciously. If the LO
source cannot provide the 0 dBm level, operation at a reduced
power below 0 dBm is acceptable. Reduced LO drive results in
slightly increased modulator noise. The effect of LO power on
sideband suppression and carrier feedthrough is shown in
Figure 19. The effect of LO power on GSM noise is shown in
Figure 33.
RF OUTPUT
The RF output is available at the VOUT pin (Pin 13). The
VOUT pin connects to an internal balun, which is capable of
driving a 50 Ω load. For applications requiring 50 Ω output
impedance, external matching is needed (see Figure 8 for S22
performance). The internal balun provides a low dc path to
ground. In most situations, the VOUT pin should be ac-coupled
to the load.
ADL5371