ADN2891ACPZ-WP Analog Devices Inc, ADN2891ACPZ-WP Datasheet

APC12.7Gbps Limiting Amplifier.I.C.

ADN2891ACPZ-WP

Manufacturer Part Number
ADN2891ACPZ-WP
Description
APC12.7Gbps Limiting Amplifier.I.C.
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADN2891ACPZ-WP

Amplifier Type
Limiting
Number Of Circuits
1
Output Type
Differential
Voltage - Input Offset
100µV
Current - Supply
45mA
Voltage - Supply, Single/dual (±)
2.9 V ~ 3.6 V
Operating Temperature
-40°C ~ 95°C
Mounting Type
Surface Mount
Package / Case
16-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output / Channel
-
-3db Bandwidth
-
Slew Rate
-
Gain Bandwidth Product
-
Current - Input Bias
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
Input sensitivity: 4 mV p-p
80 ps rise/fall times
CML outputs: 700 mV p-p differential
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
Single-supply operation: 3.3 V
Low power dissipation: 145 mW
Available in space-saving 3 mm × 3 mm, 16-lead LFCSP
Extended temperature range: −40°C to +95°C
SFP reference design available
APPLICATIONS
SFP/SFF/GBIC optical transceivers
OC-3/OC-12/OC-48, GbE, Fibre Channel (FC) receivers
10GBASE-LX4 transceivers
WDM transponders
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SFF-8472-compliant average power measurement
ADN2880
PD_CATHODE
PD_VCC
PIN
NIN
FUNCTIONAL BLOCK DIAGRAM
CAZ1
50Ω
ADN2891
AVCC
0.01
50Ω
μ
3kΩ
AVEE
F
Figure 1.
CAZ2
V
REF
DETECTOR
RSSI/LOS
DRVCC
GENERAL DESCRIPTION
The ADN2891 is a 3.2 Gbps limiting amplifier with integrated
loss-of-signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for SONET,
Gigabit Ethernet (GbE), and Fibre Channel optoelectronic
conversion applications. The ADN2891 has a differential input
sensitivity of 4 mV p-p and accepts up to a 2.0 V p-p differential
input overload voltage. The ADN2891 supports current mode
logic (CML) outputs with controlled rise and fall times.
By monitoring the bias current through a photodiode, the on-
chip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472-
compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch.
The ADN2891 is available in a 3 mm × 3 mm, 16-lead LFCSP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
DRVCC
THRADJ
50Ω
DRVEE
SQUELCH
50Ω
LOS
RSSI_OUT
©2005 Analog Devices, Inc. All rights reserved.
OUTP
OUTN
+V
Limiting Amplifier
10k
Ω
3.3 V, 3.2 Gbps,
ADuC7020
ADN2891
www.analog.com

Related parts for ADN2891ACPZ-WP

ADN2891ACPZ-WP Summary of contents

Page 1

FEATURES Input sensitivity p rise/fall times CML outputs: 700 mV p-p differential Programmable LOS detector: 3 signal strength indicator (RSSI) SFF-8472-compliant average power measurement Single-supply operation: 3.3 V Low power dissipation: ...

Page 2

ADN2891 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Limiting Amplifier ..................................................................... 10 REVISION HISTORY 7/05—Rev. ...

Page 3

SPECIFICATIONS Test Conditions: VCC = 2 3.6 V, VEE = Table 1. Parameter Min QUANTIZER DC CHARACTERISTICS Input Voltage Range 1.8 Input Common Mode 2.1 Differential Input Range Differential Input Sensitivity 5.2 Input Offset Voltage ...

Page 4

ADN2891 Parameter Min LOGIC INPUTS (SQUELCH Input High Voltage 2 Input Low Voltage IL Input Current LOGIC OUTPUTS (LOS Output High Voltage 2 Output Low Voltage OL Typ Max Unit ...

Page 5

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Power Supply Voltage Minimum Voltage (All Inputs and Outputs) Maximum Voltage (All Inputs and Outputs) Storage Temperature Operating Temperature Range Production Soldering Temperature Junction Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges ...

Page 6

ADN2891 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane with filled vias. Table 4. Pin Function Descriptions Pin ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS 50ps/DIV Figure 3. Eye of ADN2891 @ 25°C, 3.2 Gbps, and 10 mV Input 50ps/DIV Figure 4. Eye of ADN2891 @ 25°C, 3.2 Gbps, and 500 mV Input 50ps/DIV Figure 5. Eye of ADN2891 @ 95°C, 3.2 ...

Page 8

ADN2891 70 60 –40°C 50 +95°C +25°C 40 +95°C 30 +25°C DEASSERTION 20 –40°C 10 ASSERTION 0 1k 10k R (Ω) TH Figure 8. LOS Trip and Release vs 10k R (Ω) TH ...

Page 9

PD_CATHODE CURRENT (PHOTODIODE CURRENT) (μA) Figure 14. RSSI Output vs. Average Photodiode Current PD_CATHODE CURRENT (PHOTODIODE ...

Page 10

ADN2891 THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer The ADN2891 limiting amplifier provides differential inputs (PIN/NIN), each having single-ended, on-chip, 50 Ω termina- tion. The amplifier can accept either dc-coupled or ac-coupled signals; however, an ac-coupled signal is recommended. Using ...

Page 11

APPLICATIONS PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used to ensure optimal performance. Output Buffer Power Supply and Ground Planes Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and ground pins that provide current ...

Page 12

ADN2891 PCB Layout Figure 21 shows the recommended PCB layout. The 50 Ω transmission lines are the traces that bring the high frequency input and output signals (PIN, NIN, OUTP, and OUTN) to the SMA connectors with minimum reflection. To ...

Page 13

... MAX 0.90 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range ADN2891ACPZ-500RL7 1 –40°C to +95°C 1 ADN2891ACPZ-RL7 –40°C to +95°C ADN2891ACPZ-RL 1 –40°C to +95°C EVAL-ADN2891EB Pb-free part. 3.00 0.60 MAX BSC SQ 0.45 2.75 TOP BSC SQ VIEW 0.50 BSC 1 ...

Page 14

ADN2891 NOTES Rev Page ...

Page 15

NOTES Rev Page ADN2891 ...

Page 16

ADN2891 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05244–0–7/05(A) Rev Page ...

Related keywords