ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 20

• Manufacturer Part Number: ADN8102ACPZ
• Description: IC,Cable Equalizer,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN8102ACPZ

• Applications: Ethernet Controller
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 64-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN8102
LOOPBACK
The ADN8102 provides loopback on both input ports (Port A:
cable interface input, and Port B: line card interface input). The
external loopback toggle pin, LB, controls the loopback of the Port
B input only (board side loopback). When loopback is asserted,
valid data continues to pass through the Port B link, but the
Port B input signals are also shunted to the Port A output to allow
testing and debugging without disrupting valid data. This
loopback, as well as loopback of the Port A input (cable side
loopback), can be programmed through the I
loopbacks are controlled through the I
Bit 0 and Bit 1 of the loopback control register (Register 0x02).
ADDR[1:0]
Table 12. Loopback Control Functionality
Control Mode
Pin Control (00 or 01)
Serial Control
(10 or 11)
1
2
Table 13. Loopback Control Register
Name
Loopback control
Ox_A[3:0]
Ix_B[3:0]
Refer to Table 5 for additional information regarding control mode settings.
X = don’t care.
RESET
SDA
SCL
LB
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
EQ
CABLE SIDE LOOPBACK
PE
1
CONTROL LOGIC
0
LB Pin
1
X
X
X
X
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
PE
EQ
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
2
LB[1]
X
X
0
0
1
1
C interface by writing to
Address
0x02
2
2
C interface. The
ADDR[1:0]
Ox_A[3:0]
Ix_B[3:0]
RESET
SCL
SDA
LB
Bit 7
LB[0]
X
X
0
1
0
1
Figure 40. Loopback Modes of Operation
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
EQ
PE
BOARD SIDE LOOPBACK
Rev. B | Page 20 of 36
Bit 6
CONTROL LOGIC
Description
Loopback disabled
Board side loopback enabled
Loopback disabled
Cable side loopback enabled
Board side loopback enabled
Full loopback enabled
Bit 5
PRE-EMPHASIS
EQUALIZATION
Bit 0 represents loopback of the Port A inputs to the Port B
outputs (cable side loopback). Bit 1 represents loopback of the
Port B inputs to the Port A outputs (board side loopback), with
high representing loopback for both bits. Bit 1 can be overridden
by the LB pin if the pin mode register is set to enable loopback
via external pin as shown in Table 5. Both input ports can be
looped back simultaneously (full loopback) by writing high to
both Bit 0 and Bit 1, but in this case, valid data is disrupted on
each channel. Figure 40 illustrates the three loopback modes.
TRANSMIT
RECEIVE
PE
EQ
Bit 4
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
Bit 3
ADDR[1:0]
Ox_A[3:0]
Ix_B[3:0]
RESET
SDA
SCL
LB
Bit 2
EQUALIZATION
PRE-EMPHASIS
TRANSMIT
RECEIVE
EQ
PE
Bit 1
LB[1]
FULL LOOPBACK
CONTROL LOGIC
Bit 0
LB[0]
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
PE
EQ
Default
0x00
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB