ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 21

IC,Cable Equalizer,LLCC,64PIN,PLASTIC

ADN8102ACPZ

Manufacturer Part Number
ADN8102ACPZ
Description
IC,Cable Equalizer,LLCC,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
XStream™r
Datasheet

Specifications of ADN8102ACPZ

Applications
Ethernet Controller
Interface
I²C
Voltage - Supply
1.8 V ~ 3.3 V
Package / Case
64-LFCSP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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TRANSMITTERS
Output Structure and Output Levels
The ADN8102 transmitter outputs incorporate 50 Ω termina-
tion resistors, ESD protection, and an output current switch. Each
port provides control of both the absolute output level and the
pre-emphasis output level. It should be noted that the choice of
output level affects the output common-mode level. A 600 mV
peak-to-peak differential output level with full pre-emphasis
range requires an output termination voltage of 2.5 V or greater
(V
Pre-Emphasis
The total output amplitude and pre-emphasis setting space is
reduced to a single map of basic settings that provide seven
settings of output equalization to ease programming for typical
channels. The PE_A/PE_B[1:0] pins provide selections 0, 2, 4,
and 6 of the seven pre-emphasis settings through toggle pin
control, covering the entire range of settings at lower resolution.
The full resolution of seven settings is available through the I
interface by writing to Bits[2:0] (PE[2:0] of the OUT_A/OUT_B
configuration registers) with I
Table 15. Transmit Pre-Emphasis Boost and Overshoot vs. Setting
PE[2:0] Register
0
1
2
3
4
5
6
Table 16. Output Configuration Registers
Name
OUT_A/OUT_B configuration
OUT_A/OUT_B Output Level Control 1
OUT_A/OUT_B Output Level Control 0
TTO
, V
VP
V2
Tx SIMPLIFIED DIAGRAM
CC
VC
V3
≥ 2.5 V).
Figure 41. Simplified Output Structure
V1
VN
I
DC
PE[1:0] Pins
0
Not applicable
1
Not applicable
2
Not applicable
4
TERMINATION
+ I
Q1
50Ω
PE
ON-CHIP
RP
2
Q2
C settings overriding the toggle
I
TOT
RN
50Ω
Boost (dB)
0
2
3.5
4.9
6
7.4
9.5
Address
0xC0, 0xE0
0xC1, 0xE1
0xC2, 0xE2
ESD
Bit 7
PE CTL SRC
Overshoot (%)
0
25
50
75
100
133
200
V
V
OP
ON
V
CC
TTO
EE
Rev. B | Page 21 of 36
2
C
Bit 6
DC Swing
(mV p-p diff)
800
800
800
800
800
600
400
pin control. Similar to the receiver settings, the ADN8102 allows
joint control of all four channels in a transmit port. Table 15
summarizes the absolute output level, pre-emphasis level, and
high frequency boost for each of the basic control settings and
the typical length of the CX4 cable and FR4 trace that each
setting compensates.
Full control of the transmit output levels is available through the
I
the OUT_A/OUT_B Output Level Control[1:0] registers for the
channel of interest. Table 17 shows the supported output level
settings of the OUT_A/OUT_B Output Level Control[1:0]
registers. Register settings not listed in Table 17 are not
supported by the ADN8102.
The output equalization is optimized for less than 1.75 Gbps
operation but can be optimized for higher speed applications at
up to 3.75 Gbps through the I
the DATA RATE bit (Bit 4) of the OUT_A/OUT_B configuration
registers, with high representing 3.75 Gbps and low representing
1.75 Gbps. The PE CTL SRC bit (Bit 7) in the OUT_A/OUT_B
Output Level Control 1 register determines whether the pre-
emphasis and output current controls for the channel of interest
are selected from the optimized map or directly from the OUT_A/
OUT_B Output Level Control[1:0] registers (per channel). Setting
this bit high selects pre-emphasis control directly from the
OUT_A/OUT_B Output Level Control[1:0] registers, and setting
it low selects pre-emphasis control from the optimized map.
Table 14. Data Rate Select
OUT_A/OUT_B Configuration Bit 4
0 (default)
1
2
C control interface. This full control is achieved by writing to
Bit 5
EN
Bit 4
DATA RATE
OUTx_OLEV1[6:0]
OUTx_OLEV0[6:0]
Typical CX4 Cable
Length (Meters)
0 to 2.5
2.5 to 5
5 to 7.5
7.5 to 10
10 to 12.5
15 to 17.5
20 to 22.5
Bit 3
2
C control interface by writing to
Bit 2
PE[2]
Bit 1
PE[1]
Supported Data Rates
0 Gbps to 1.75 Gbps
1.75 Gbps to 3.75 Gbps
Typical FR4 Trace
Length (Inches)
0 to 5
0 to 5
10 to 15
10 to 15
15 to 20
20 to 25
25 to 30
Bit 0
PE[0]
ADN8102
Default
0x20
0x40
0x40

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