ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 24

• Manufacturer Part Number: ADN8102ACPZ
• Description: IC,Cable Equalizer,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN8102ACPZ

• Applications: Ethernet Controller
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 64-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN8102
SELECTIVE SQUELCH AND DISABLE
Each transmitter is equipped with output disable and output
squelch controls. Disable is a full power-down state: the trans-
mitter current is reduced to zero, and the output pins pull up
to V
with re-enabling the transmitter. The output disable control is
accessed through the EN bit (Bit 4) of the OUT_A/OUT_B
configuration registers through the I
Squelch is not a full power-down state but a state in which only
the output current is reduced to zero and the output pins pull
up to V
output current. The output squelch and the output disable control
can both be accessed through the OUT_A/OUT_B squelch
control registers, with the top nibble representing the squelch
control for one entire output port, and the bottom nibble
representing the output disable for one entire output port. The
ports are disabled or squelched by writing 0s to the corresponding
nibbles. The ports are enabled by writing all 1s, which is the
TTO
, but there is a delay of approximately 1 μs associated
TTO
, and there is a much smaller delay to bring back the
2
C control interface.
Rev. B | Page 24 of 36
default setting. For example, to squelch Port A, Register 0xC3
must be set to 0x0F. The entire nibble must be written to all 0s
for this functionality.
Table 18. Squelch and Disable Control Registers
Name
OUT_A/
OUT_B
squelch
control
Table 19. Squelch and Disable Functionality
SQUELCH[3:0]
1111
xxxx
0000
1
xxxx = don’t care
1
Address
0xC3,
0xE3
DISABLE[3:0]
1111
0000
1111
SQUELCH[3:0]
Output State
Enabled (default)
Disabled
Squelched
Data
DISABLE[3:0]
Default
0xFF