ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 27

• Manufacturer Part Number: ADN8102ACPZ
• Description: IC,Cable Equalizer,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN8102ACPZ

• Applications: Ethernet Controller
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 64-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
OUTPUT COMPLIANCE
In low voltage applications, users must pay careful attention
to both the differential and common-mode signal levels. The
choice of output voltage swing, preemphasis setting, supply
voltages (V
peak and settled single-ended voltage swings and the common-
mode shift measured across the output termination resistors.
These choices also affect output current and, consequently,
power consumption. For ac-coupled applications, certain
combinations of supply voltage, output voltage swing, and
preemphasis settings may violate the single-ended absolute output
low voltage, as specified in Table 1. Under these conditions,
the performance is degraded; therefore, these settings are not
recommended. Table 21 includes annotations that identify these
settings. In dc-coupled applications, the far-end termination voltage
should be equal to V
preemphasis settings listed in Table 17.
Table 20. Symbol Definitions
Symbol
I
I
I
V
V
V
V
∆V
∆V
V
V
V
V
V
DC
PE
TTO
DPP-DC
DPP-PE
SW-DC
SW-PE
OCM
H-DC
L-DC
H-PE
L-PE
OCM_DC-COUPLED
OCM_AC-COUPLED
CC
and V
TTO
TTO
), and output coupling (ac or dc) affect
to allow the full list of output swing and
Formula
Programmable
Programmable
I
25 Ω × I
25 Ω × I
V
V
25 Ω × I
50 Ω × I
V
V
V
V
V
DC
DPP-DC
DPP-PE
TTO
TTO
TTO
TTO
TTO
+ I
− ∆V
− ∆V
− ∆V
− ∆V
− ∆V
PE
/2 = V
/2 = V
DC
TTO
TTO
TTO
OCM
OCM
OCM
OCM
OCM
× 2
/2
/2
× 2
H-PE
H-DC
= ( V
+ V
− V
+ V
− V
– V
– V
DPP-DC
DPP-DC
DPP-PE
DPP-PE
H-DC
L-PE
L-DC
+ V
/2
/2
/2
/2
L-DC
)/2
Rev. B | Page 27 of 36
TxHeadroom
The TxHeadroom register (Register 0x23) allows configuration
of the individual transmitters for extra headroom at the output
for high current applications. The bits in this register are active
high (default) and are one per output (see Table 22). Setting a
bit high puts the respective transmitter in a configuration for
extra headroom, and setting a bit low does not provide extra
headroom. The TxHeadroom bits should only be set high when
required for a given output swing as listed in Table 21. Note that
TxHeadroom is not available for V
V
V
OCM
TTO
Definition
Output current that sets output level
Output current for PE delayed tap
Total transmitter output current
Peak-to-peak differential voltage swing of
nonpreemphasized waveform
Peak-to-peak differential voltage swing of preemphasized
waveform
DC single-ended voltage swing
Preemphasized single-ended voltage swing
Output common-mode shift, dc-coupled outputs
Output common-mode shift, ac-coupled outputs
Output common-mode voltage
DC single-ended output high voltage
DC single-ended output low voltage
Maximum single-ended output voltage
Minimum single-ended output voltage
Figure 44. Simplified Output Voltage Levels Diagram
t
PE
CC
< 2.5 V.
V
V
SW-DC
V
H-DC
L-DC
ADN8102
V
SW-PE
V
V
H-PE
L-PE