ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 30

• Manufacturer Part Number: ADN8102ACPZ
• Description: IC,Cable Equalizer,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN8102ACPZ

• Applications: Ethernet Controller
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 64-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN8102
Stencil Design for the Thermal Paddle
To effectively remove heat from the package and to enhance
electrical performance, the thermal paddle must be soldered
(bonded) to the PCB thermal paddle, preferably with minimum
voids. However, eliminating voids may not be possible because
of the presence of thermal vias and the large size of the thermal
paddle for larger size packages. Also, outgassing during the
reflow process may cause defects (splatter, solder balling) if the
solder paste coverage is too big. It is recommended that smaller
multiple openings in the stencil be used instead of one big
opening for printing solder paste on the thermal paddle region.
This typically results in 50% to 80% solder paste coverage.
Figure 47 shows how to achieve these levels of coverage.
Voids within solder joints under the exposed paddle can have
an adverse affect on high speed and RF applications, as well as
on thermal performance. Because the LFCSP package incor-
porates a large center paddle, controlling solder voiding within
this region can be difficult. Voids within this ground plane can
increase the current path of the circuit. The maximum size for a
void should be less than via pitch within the plane. This assures
that any one via is not rendered ineffectual when any void
increases the current path beyond the distance to the next
available via.
Figure 47. Typical Thermal Paddle Stencil Design
1.35mm × 1.35mm SQUARES
AT 1.65mm PITCH
COVERAGE: 68%
Rev. B | Page 30 of 36
Large voids in the thermal paddle area should be avoided. To
control voids in the thermal paddle area, solder masking may be
required for thermal vias to prevent solder wicking inside the
via during reflow, thus displacing the solder away from the
interface between the package thermal paddle and thermal
paddle land on the PCB. There are several methods employed
for this purpose, such as via tenting (top or bottom side), using
dry film solder mask; via plugging with liquid photo-imagible
(LPI) solder mask from the bottom side; or via encroaching.
These options are depicted in Figure 48. In case of via tenting,
the solder mask diameter should be 100 microns larger than the
via diameter.
A stencil thickness of 0.125 mm is recommended for 0.4 mm and
0.5 mm pitch parts. The stencil thickness can be increased to
0.15 mm to 0.2 mm for coarser pitch parts. A laser-cut, stainless
steel stencil is recommended with electropolished trapezoidal
walls to improve the paste release. Because not enough space is
available underneath the part after reflow, it is recommended
that no clean Type 3 paste be used for mounting the LFCSP.
Inert atmosphere is also recommended during reflow.
Top; (b) Via Tenting from the Bottom; (c) Via Plugging, Bottom; and (d) Via
Figure 48. Solder Mask Options for Thermal Vias: (a) Via Tenting from the
(A)
SOLDER
MASK
Encroaching, Bottom
(B)
VIA
(C)
COPPER
PLATING
(D)