ADP5020CP-EVALZ Analog Devices Inc, ADP5020CP-EVALZ Datasheet - Page 21

• Manufacturer Part Number: ADP5020CP-EVALZ
• Description: EB PMU For Digital Imaging Module
• Manufacturer: Analog Devices Inc

Specifications of ADP5020CP-EVALZ

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 3, Non-Isolated
• Voltage - Output: 3.3V, 1.2V, 1.8V
• Current - Output: 600mA, 250mA, 150mA
• Voltage - Input: 2.4 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 3MHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP5020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
POWER GOOD STATUS
The ADP5020 constantly monitors the operating conditions.
When a regulator is activated, it checks if the output voltage
level is above 80% (the power good threshold) of the nominal
level for that output. If the output voltage does not reach the
power good threshold, one of the three power good status bits in
the REG_CONTROL_STATUS register (Address 0x03) is cleared.
If the output voltage reaches the power good threshold, one of
the power good status bits in the REG_CONTROL_STATUS
register is set to 1. The REG_CONTROL_STATUS register
contains the following three power good bits: BK1_PGOOD for
the Buck 1 output (Bit 3), BK2_PGOOD for the Buck 2 output
(Bit 2), and LDO_PGOOD for the LDO output (Bit 1).
XSHTDN LOGIC
In addition to the power good information for each enabled
regulator, an XSHTDN signal is generated, as shown in Table 18. If
one or more regulators are unused in a specific application, the
masking bits for the disabled regulator, which are fuse pro-
grammable and I
set to 1 to mask the status of the power good signal. Besides having
the masking bits predefined through factory-programmed fuses
(necessary only for operation with the EN signal), the ADP5020
provides three masking bits that are accessible through the I
interface. These bits are located in the OPERATIONAL_
CONTROL register (Address 0x04), where the BK1_XSHTDN
bit (Bit 3) is the mask (if set to 1) for Buck 1, the BK2_XSHTDN bit
(Bit 2) is the mask (if set to 1) for Buck 2, and the LDO_
XSHTDN bit (Bit 3) is the mask (if set to 1) for the LDO. Addi-
tional failures that are verified are the input (VDDA) undervoltage
condition, as described in the Undervoltage Lockout section; and
an overtemperature condition of the die, as described in the
Thermal Shutdown section. As soon as one of these conditions
occurs, the active regulators are immediately turned off, and the
XSHTDN pin is set to 0.
COMPONENTS SELECTION
Buck Inductor
The buck inductor is chosen to meet output ripple current and
ripple voltage requirements with minimum size. The fast load
transient response and wide frequency bandwidth are also impor-
tant factors for inductor selection. The minimum inductance of the
buck converter is derived from the following equation:
where:
V
V
f
r is the inductor ripple factor, which is selected as 30%.
SW
INMAX
OUT
is the converter switching frequency.
L
is the regulator output voltage in the buck converter.
MINBUCK
is the maximum input supply voltage.
=
(
V
V
2
C programmable after device startup, must be
INMAX
INMAX
×
−
f
V
SW
OUT
×
)
r
×
×
V
I
OUT
OUT
2
C
Rev. 0 | Page 21 of 28
(1)
Peak inductor current is calculated in the following equation:
The calculated minimum Buck 2 inductor value is 2.2 μH. The
maximum peak inductor current is 325 mA. A ceramic inductor
such as the Taiyo Yuden BRL2012T2R2M, with a 600 mA satu-
ration current in a 2 mm × 1.2 mm × 1 mm package, can be used.
For the Buck 1 converter, the calculated minimum inductance is
2.2 μH, with maximum peak current of 690 mA. A ceramic
inductor such as the Taiyo Yuden BRL2518T2R2M, with a 1 A
saturation current in a 2.5 mm × 1.8 mm × 1.2 mm package, is
recommended.
Input Capacitor Selection
The input capacitors are used to decouple the parasitic inductance
of input wires to the converters and to reduce the input ripple
voltage and the switching ac current flow to the battery rail. The
capacitors are selected to support the maximum input operating
voltage and the maximum rms current. The capacitance must also
be large enough to ensure input stability and suppress input ripple.
ESR should as small as possible to decouple the noise. MLCC
ceramic capacitors are a good choice for battery-powered appli-
cations because of their high capacitance, small size, and low ESR.
A 10 μF ceramic capacitor (for example, the JMK107BJ106MA-T
from Taiyo Yuden) is recommended.
Output Capacitor Selection
Output capacitor selection should be based on the following three
factors:
•
•
•
Note that the output ripple is the combination of several factors,
including the inductor ripple current (ΔI
output capacitors, and the capacitor impedance at the switching
frequency.
In buck converters, the output ripple can be calculated as
follows:
Capacitor manufacturer data sheets show the ESR and ESL
value. In real-life applications, the ripple voltage may be higher
because the equations provided in this data sheet do not consider
parameters such as board/package parasitic inductance and
capacitance. The minimum recommended capacitance is no less
than 4.0 μF for Buck 1, 2.0 μF for Buck 2, and 0.4 μF for the
LDO.
I
Maximizing the control loop bandwidth of the converter
with the LC filter
Minimizing the output voltage ripple
Minimizing the size of the capacitor
ΔV
ΔI
LMAX
L
OUTRIPPLE
= r × I
= I
OUT
OUT
= ΔI
+ 0.5 × r × I
L
⎛
⎜
⎜
⎝
ESR
+
8
OUT
×
f
SW
1
×
C
OUT
L
), the ESR and ESL
+
4
×
ESL
ADP5020
×
f
SW
⎞
⎟
⎟
⎠
(2)