ADP5020CP-EVALZ Analog Devices Inc, ADP5020CP-EVALZ Datasheet - Page 7

• Manufacturer Part Number: ADP5020CP-EVALZ
• Description: EB PMU For Digital Imaging Module
• Manufacturer: Analog Devices Inc

Specifications of ADP5020CP-EVALZ

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 3, Non-Isolated
• Voltage - Output: 3.3V, 1.2V, 1.8V
• Current - Output: 600mA, 250mA, 150mA
• Voltage - Input: 2.4 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 3MHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP5020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Table 6.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
Timing Diagram
SCL
2
HIGH
LOW
SU,DAT
HD,DAT
SU,STA
HD,STA
BUF
SU,STO
RISE
FALL
SP
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
C
B
C TIMING SPECIFICATIONS
2
B
is the total capacitance of one bus line in picofarads (pF).
1
SDA
S = START CONDITION
Sr = START REPEATED CONDITION
P = STOP CONDITION
SCL
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20 + 0.1C
20 + 0.1C
0
S
B
B
t
LOW
Max
400
0.9
300
300
50
400
t
HD,DAT
t
RISE
Unit
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
ns
ns
pF
t
SU,DAT
Figure 3. I
Description
SCL clock frequency
SCL high time
SCL low time
Data setup time
Data hold time
Setup time for repeated start
Hold time for start/repeated start
Bus free time between a stop condition and a start condition
Setup time for stop condition
Rise time of SCL/SDA
Fall time of SCL/SDA
Pulse width of suppressed spike
Capacitive load for each bus line
t
HIGH
2
Rev. 0 | Page 7 of 28
C Interface Timing Diagram
t
t
SU,STA
FALL
Sr
IHMIN
of the SCL signal) to bridge the undefined region of the SCL falling edge.
t
FALL
t
HD,STA
t
t
SP
SU,STO
t
RISE
P
t
BUF
S
ADP5020