Digital Signal Processor(DSP) IC

ADSP-2101BG-100

Manufacturer Part NumberADSP-2101BG-100
DescriptionDigital Signal Processor(DSP) IC
ManufacturerAnalog Devices Inc
SeriesADSP-21xx
TypeFixed Point
ADSP-2101BG-100 datasheet
 


Specifications of ADSP-2101BG-100

Rohs StatusRoHS non-compliantInterfaceSynchronous Serial Port (SSP)
Clock Rate25MHzNon-volatile MemoryExternal
On-chip Ram6kBVoltage - I/o5.00V
Voltage - Core5.00VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case68-PGA
Package68CPGANumeric And Arithmetic FormatFixed-Point
Maximum Speed25 MHzRam Size3 KB
Device Million Instructions Per Second25 MIPS  
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SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer,
Host Interface Port (ADSP-2111 Only)
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
ADSP-2111 Host Interface Port Provides Easy Interface
to 68000, 80C51, ADSP-21xx, Etc.
Automatic Booting of ADSP-2111 Program Memory
Through Host Interface Port
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available
GENERAL DESCRIPTION
The ADSP-2100 Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture—computation
units, data address generators, and program sequencer—with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADSP-2100 Family
DSP Microcomputers
FUNCTIONAL BLOCK DIAGRAM
MEMORY
DATA ADDRESS
PROGRAM
GENERATORS
PROGRAM
SEQUENCER
MEMORY
DAG 1
DAG 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
SERIAL PORTS
ARITHMETIC UNITS
MAC
ALU
SHIFTER
SPORT 0
SPORT 1
ADSP-2100 CORE
This data sheet describes the following ADSP-2100 Family
processors:
ADSP-2101
ADSP-2103
3.3 V Version of ADSP-2101
ADSP-2105
Low Cost DSP
ADSP-2111
DSP with Host Interface Port
ADSP-2115
ADSP-2161/62/63/64 Custom ROM-programmed DSPs
The following ADSP-2100 Family processors are not included
in this data sheet:
ADSP-2100A
DSP Microprocessor
ADSP-2165/66
ROM-programmed ADSP-216x processors
with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)
ADSP-21msp5x
Mixed-Signal DSP Processors with
integrated on-chip A/D and D/A plus
powerdown
ADSP-2171
Speed and feature enhanced ADSP-2100
Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking
ADSP-2181
ADSP-21xx processor with ADSP-2171
features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.
Refer to the individual data sheet of each of these processors for
further information.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
ADSP-21xx
FLAGS
(ADSP-2111)
DATA
MEMORY
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
HOST
TIMER
INTERFACE
PORT
(ADSP-2111)
© Analog Devices, Inc., 1996
Fax: 617/326-8703

ADSP-2101BG-100 Summary of contents

  • Page 1

    ... The ADSP-2100 Family processors are single-chip micro- computers optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-21xx processors are all built upon a common core. Each processor combines the core DSP architecture—computation units, data address generators, and program sequencer—with ...

  • Page 2

    ... Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Supply Current & Power (ADSP-2101/2161/2163 Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 19 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 19 Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPECIFICATIONS (ADSP-2111 Recommended Operating Conditions . . . . . . . . . . . . . . . . 21 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 23 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 23 • Receive and transmit data via one or two serial ports • ...

  • Page 3

    ... PLCC 80-Lead PQFP 80-Lead TQFP 100-Pin PGA 100-Lead PQFP Temperature Grades K Commercial + Industrial T Extended Table II. ADSP-216x ROM-Programmed Processor Features Feature Data Memory (RAM) Program Memory (ROM) Program Memory (RAM) Timer Serial Port 0 (Multichannel) Serial Port 1 Supply Voltage Speed Grades (Instruction Cycle Time) 10 ...

  • Page 4

    ... Program memory can store both instructions and data, permit- ting the ADSP-21xx to fetch two operands in a single cycle, one from program memory and one from data memory. The processor can fetch an operand from on-chip program memory and the next instruction in the same cycle ...

  • Page 5

    ... Booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. After reset, three wait states are automatically generated. This allows, for example ADSP-2101 to use a 200 ns EPROM as external boot memory. Multiple programs can be selected and loaded from the EPROM with no additional hardware. ...

  • Page 6

    ... Host Interface Port (ADSP-2111) The ADSP-2111 includes a Host Interface Port (HIP), a parallel I/O port that allows easy connection to a host processor. Through the HIP, the ADSP-2111 can be accessed by the host processor as a memory-mapped peripheral. The host interface port can be thought area of dual-ported memory, or mailbox registers, that allows communication between the computational core of the ADSP-2111 and the host computer ...

  • Page 7

    ... ADSP-2101 and ADSP-2103. A total of 14.5K words of data memory and 15K words of program memory is addressable for the ADSP-2115. Figure 4 shows a system diagram for the ADSP-2105, with one serial I/O device, a boot EPROM, and optional external program and data memory. A total of 14.5K words of data memory and 15K words of program memory is addressable for the ADSP-2105 ...

  • Page 8

    ... BR must be tied high ( not used ADSP-2105 does not have SPORT0. (SPORT0 pins are No Connects on the ADSP-2105.) The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid V applied to the processor and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency ...

  • Page 9

    ... SERIAL DEVICE (OPTIONAL) SERIAL DEVICE (OPTIONAL) THE TWO MSBs OF THE DATA BUS (D BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512. Figure 3. ADSP-2101/ADSP-2103/ADSP-2115 System 1x CLOCK or CRYSTAL SERIAL DEVICE (OPTIONAL) THE TWO MSBs OF THE DATA BUS (D BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512. ...

  • Page 10

    ... The external address bus is 14 bits wide. For the ADSP-2101, ADSP-2103, and ADSP-2111, these lines can directly address up to 16K words, of which 2K are on-chip. For the ADSP-2105 and ADSP-2115, the address lines can directly address up to 15K words, of which 1K is on-chip. ...

  • Page 11

    ... In this configuration, program memory is not booted although it can be written to and read under program control. 0x0000 EXTERNAL 14K 0x37FF 0x3800 INTERNAL RAM 2K 0x3FFF MMAP=1 No Booting Figure 8. ADSP-2105/ADSP-2115 Program Memory Maps 0x0000 2K EXTERNAL 0x07FF 0x0800 6K INTERNAL ROM 0x1FF0 RESERVED 0x1FFF 0x2000 6K ...

  • Page 12

    ... The boot memory interface can generate zero to seven wait states; it defaults to three wait states after RESET. This allows the ADSP-21xx to boot from a single low cost EPROM such as a 27C256. Program memory is booted one byte at a time and converted to 24-bit program memory words. ...

  • Page 13

    ... IDLE state is in- creased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21xx will remain in the IDLE state for maximum of n CLKIN cycles (where n = 16, 32, 64, or 128) before resuming normal operation. ...

  • Page 14

    ... BG is asserted in the cycle after BR is recognized.) • Only the standard IDLE instruction is available, not the clock-reducing IDLE n instruction. To determine the revision of a particular ADSP-21xx device, inspect the marking on the device. For example, an ADSP-2101 of revision 6.0 will have the following marking: a ADSP-2101 KS-66 EE/A12345-6.0 ...

  • Page 15

    ... Instruction Set The ADSP-21xx assembly language uses an algebraic syntax for ease of coding and readability. The sources and destinations of computations and data movements are written explicitly in each assembly statement, eliminating cryptic assembler mnemonics. Every instruction assembles into a single 24-bit word and executes in a single cycle. The instructions encompass a wide ...

  • Page 16

    ... ADSP-21xx Program Flow Instructions DO <addr> [UNTIL term] ; [IF cond] JUMP (Ix) ; [IF cond] JUMP <addr>; [IF cond] CALL (Ix) ; [IF cond] CALL <addr>; IF [NOT ] FLAG_IN JUMP <addr>; IF [NOT ] FLAG_IN CALL <addr>; [IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ; [IF cond] RTS ; [IF cond] RTI ; IDLE [(n)] ; Miscellaneous Instructions NOP ; MODIFY (Ix , My); [PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ; ...

  • Page 17

    ... Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0 (not on ADSP-2105), RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105). 4 Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0 (not on ADSP-2105), SCLK0 (not on ADSP-2105), RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105). 5 Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105). ...

  • Page 18

    ... Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V 4 ADSP-2105 is not available MHz speed grade. For typical supply current (internal power dissipation) figures, see Figure 11. IDD IDLE 70 ...

  • Page 19

    ... load capacitance output switching frequency. Example ADSP-2101 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • ...

  • Page 20

    ... ADSP-21xx SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163) TEST CONDITIONS Figure 14 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 14. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...

  • Page 21

    ... Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1- BR, CLKIN Active (to force tristate condition). 7 Although specified for TTL outputs, all ADSP-2111 outputs are CMOS-compatible and will drive Guaranteed but not tested. 9 Applies to ADSP-2111 PGA and PQFP packages. ...

  • Page 22

    ... Supply Current (Idle) DD NOTES 1 Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V For typical supply current (internal power dissipation) figures, see Figure 17. POWER, IDLE 100 80mW 80 70 ...

  • Page 23

    ... load capacitance output switching frequency. Example ADSP-2111 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • ...

  • Page 24

    ... ADSP-21xx SPECIFICATIONS (ADSP-2111) TEST CONDITIONS Figure 20 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 20. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...

  • Page 25

    ... Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0 BR, CLKIN Active (to force tristate condition). 6 All ADSP-2103, ADSP-2162, and ADSP-2164 outputs are CMOS and will drive Guaranteed but not tested. 8 Applies to PLCC and PQFP package types. ...

  • Page 26

    ... I Supply Current (Idle) DD NOTES 1 Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V For typical supply current (internal power dissipation) figures, see Figure 23 9mW 3.30V DD 6mW 6 5mW ...

  • Page 27

    ... load capacitance output switching frequency. Example ADSP-2103 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • ...

  • Page 28

    ... ADSP-21xx SPECIFICATIONS (ADSP-2103/2162/2164) TEST CONDITIONS Figure 26 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 26. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...

  • Page 29

    ... Timing requirements guarantee that the processor operates correctly with other devices. MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP-21xx timing parameters, for your convenience. ADSP-21xx Timing Timing ...

  • Page 30

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163) CLOCK SIGNALS & RESET 13 MHz Parameter Min Timing Requirement: t CLKIN Period 76 CLKIN Width Low 20 CKL t CLKIN Width High 20 CKH t RESET Width Low 384.5 RSP Switching Characteristic: t CLKOUT Width Low 28.5 CPL t CLKOUT Width High 28.5 CPH t CLKIN High to CLKOUT 0 ...

  • Page 31

    ... IFS IFH during the following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 3 Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced. ...

  • Page 32

    ... Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors asserted in the cycle after BR is recognized ...

  • Page 33

    ... TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163) MEMORY READ Parameter Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High to RD Low CRD t A0–A13, PMS, DMS, BMS Setup before ...

  • Page 34

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163) MEMORY WRITE Parameter Switching Characteristic: t Data Setup before WR High DW t Data Hold after WR High Pulse Width Low to Data Enabled WDE t A0–A13, DMS, PMS Setup before ASW WR Low t Data Disable before Low DDR t CLKOUT High to WR Low ...

  • Page 35

    ... TFS (Alt Valid TDV t SCLK High to DT Disable SCDD t RFS (Multichannel, Frame Delay Zero) RDV to DT Valid *Maximum serial port operating frequency is 13.824 MHz for all processor speed grades except the 12.5 MHz ADSP-2101 and 13.0 MHz ADSP-2111. CLKOUT SCLK DR RFS IN TFS IN RFS ...

  • Page 36

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2111) HOST INTERFACE PORT Separate Data & Address (HMD1 = 0 ) Read Strobe & Write Strobe (HMD0 = 0) Parameter Timing Requirement: t HA2-0 Setup before Start of Write or Read HSU t Data Setup before End of Write HDSU 3 t Data Hold after End of Write HWDH ...

  • Page 37

    ... HD15–0 HA2–0 HSEL HRD Host Read Cycle HACK HD15–0 Figure 35. Host Interface Port (HMD1 = 0, HMD0 = 0) REV. B ADDRESS t HRWP t HSU HSHK HKH DATA t HDSU ADDRESS t HRWP t HSU HSHK HKH DATA t t HDE HRDH t t HRDD HDD –37– ADSP-21xx t HWDH ...

  • Page 38

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2111) HOST INTERFACE PORT Separate Data & Address (HMD1 = 0) Read/Write Strobe & Data Strobe (HMD0 = 1) Parameter Timing Requirement: t HA2-0, HRW Setup before Start of Write or Read HSU t Data Setup before End of Write HDSU 2 t Data Hold after End of Write ...

  • Page 39

    ... HD15–0 HA2–0 HSEL HRW Host Read Cycle HDS HACK HD15–0 REV. B ADDRESS t HRWP t HSU t HSHK DATA t HDSU ADDRESS t HRWP t HSU t HSHK DATA t HDE t HDD Figure 36. Host Interface Port (HMD1 = 0, HMD0 =1) –39– ADSP-21xx HKH t HWDH HKH t HRDH t HRDD ...

  • Page 40

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2111) HOST INTERFACE PORT Multiplexed Data & Address (HMD1 = 1) Read Strobe & Write Strobe (HMD0 = 0) Parameter Timing Requirement: t ALE Pulse Width HALP t HAD15-0 Address Setup before ALE Low HASU t HAD15-0 Address Hold after ALE Low HAH t Start of Write or Read after ALE Low ...

  • Page 41

    ... Host Read Cycle HRD HACK HAD15–0 Figure 37. Host Interface Port (HMD1 = 1, HMD0 = 0) REV HALP t HRWP t HALS t HSHK t t HASU HAH ADDRESS DATA t HDSU t HALP t HRWP t HALS t HSHK t t HASU HAH t HDE ADDRESS t HDD –41– ADSP-21xx t HKH t HWDH t HKH DATA t HRDH t HRDD ...

  • Page 42

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2111) HOST INTERFACE PORT Multiplexed Data & Address (HMD1 = 1) Read/Write Strobe & Data Strobe (HMD0 = 1 ) Parameter Timing Requirement: t ALE Pulse Width HALP t HAD15-0 Address Setup before ALE Low HASU t HAD15-0 Address Hold after ALE Low HAH t Start of Write or Read after ALE Low ...

  • Page 43

    ... HD15–0 Figure 38. Host Interface Port (HMD1 = 1, HMD0 = 1) REV HALP t HRWP t HALS t HSU t HSHK t t HASU HAH ADDRESS t HDSU t HALP t t HALS HRWP t HSU t HSHK t t HASU HAH t HDE ADDRESS t HDD –43– ADSP-21xx HKH DATA t HWDH HKH DATA t HRDH t HRDD ...

  • Page 44

    ... Timing requirements guarantee that the processor operates correctly with other devices. MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP-21xx timing parameters, for your convenience. ADSP-21xx Timing Parameter Timing Parameter Definition t A0– ...

  • Page 45

    ... TIMING PARAMETERS (ADSP-2103/2162/2164) CLOCK SIGNALS & RESET Parameter Timing Requirement: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t RESET Width Low RSP Switching Characteristic: t CLKOUT Width Low CPL t CLKOUT Width High CPH t CLKIN High to CLKOUT High CKOH NOTES 1 Applies after powerup sequence is complete ...

  • Page 46

    ... IFS IFH following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 3 Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced. ...

  • Page 47

    ... Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors asserted in the cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal. ...

  • Page 48

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2103/2162/2164) MEMORY READ Parameter Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High to RD Low CRD t A0–A13, PMS, DMS, BMS Setup before RD Low ...

  • Page 49

    ... TIMING PARAMETERS (ADSP-2103/2162/2164) MEMORY WRITE Parameter Switching Characteristic: t Data Setup before WR High DW t Data Hold after WR High Pulse Width Low to Data Enabled WDE t A0–A13, DMS, PMS Setup before WR Low ASW t Data Disable before Low DDR t CLKOUT High to WR Low CWR t A0– ...

  • Page 50

    ... ADSP-21xx TIMING PARAMETERS (ADSP-2103/2162/2164) SERIAL PORTS Parameter Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP in Switching Characteristic: t CLKOUT High to SCLK CC out t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...

  • Page 51

    ... K1 V D18 –51– ADSP-21xx D20 D22 V BR RESET MMAP IRQ2 D21 D23 A6 INDEX A7 (NC) A9 PGA PACKAGE A11 ADSP-2101 A13 DMS BOTTOM VIEW (PINS UP) BG CLK IN IRQ1 FI SCLK0 GND TFS0 (TFS1) (DR1) IRQ0 FO D0 SCLK1 DR0 RFS0 DT0 WR (RFS1) (DT1 CONNECT ...

  • Page 52

    ... ADSP-2105) A10 51 SCLK0 (NC on ADSP-2105) A11 –52– SCLK1 55 FI (DR1) 54 IRQ0 (RFS1) 53 IRQ1 (TFS1 (DT1) 51 SCLK0 (NC on ADSP-2105) 50 DR0 (NC on ADSP-2105) 49 GND 48 RFS0 (NC on ADSP-2105) 47 TFS0 (NC on ADSP-2105) 46 DT0 (NC on ADSP-2105 CONNECT PLCC Pin Number Name 52 FO (DT1) 53 IRQ1 (TFS1) 54 ...

  • Page 53

    ... D8 DR0 49 D9 SCLK0 50 D10 FO (DT1) 51 D11 IRQ1 (TFS1) 52 GND IRQ0 (RFS1) 53 GND FI (DR1) 54 D12 SCLK1 55 D13 V 56 D14 D15 D1 58 D16 D2 59 D17 D3 60 D18 –53– ADSP-21xx 60 D18 59 D17 58 D16 57 D15 56 D14 55 D13 54 D12 53 GND 52 GND 51 D11 50 D10 CONNECT ...

  • Page 54

    ... D10 D12 D13 D16 D18 D20 D11 D14 D17 D19 D22 D8 GND D15 PGA PACKAGE FO ADSP-2111 RD (DT1) A1 RFSO A5 HACK BOTTOM VIEW (PINS UP) INDEX PIN XTAL HD7 HD9 (NC) V HA1 HD1 HD3 HD4 HD8 HD11 HD13 HD15 DD CLK HD0 HD2 HD5 HD6 ...

  • Page 55

    ... HD15 66 HRD/HRW HD14 67 HSIZE HD13 68 HMD1 HD12 69 HMD0 HD11 70 BMODE HD10 71 IRQ2 HD9 72 HACK HD8 73 CLKOUT GND 74 DT0 V 75 TFS0 DD –55– ADSP-21xx 88 VDD 87 FL2 86 FL1 85 FL0 84 SCLK1 83 FI (DR1) 82 IRQ0 (RFS1) 81 IRQ1 (TFS1 (DT1) 79 GND 78 SCLK0 77 DR0 76 RFS0 75 TFS0 74 DT0 73 ...

  • Page 56

    ... ADSP-21xx PGA LOCATION A1 QUADRANT MARKING D A SEATING PLANE b SYMBOL OUTLINE DIMENSIONS ADSP-2101 68-Pin Grid Array (PGA) GUIDE PIN ONLY TOP VIEW INCHES MILLIMETERS MIN TYP MAX MIN 0.123 0.164 3.12 0.50 0.016 0.018 0.020 0.050 1.086 1.110 27.58 0.988 1.012 25.10 ...

  • Page 57

    ... ADSP-21xx BOTTOM VIEW (PINS UP) MILLIMETERS TYP MAX 4.29 14.37 4.45 12.64 0.43 10.46 ...

  • Page 58

    ... E 13.90 14.00 14. 12.35 12. 0.65 0.80 0.95 e 0.57 0.65 0.73 B 0.22 0.30 0.38 0.10 OUTLINE DIMENSIONS ADSP-21xx 80-Lead Metric Plastic Quad Flatpack (PQFP) 80-Lead Metric Thin Quad Flatpack (TQFP TOP VIEW (PINS DOWN PQFP INCHES MIN TYP MAX MIN 0.096 0.010 ...

  • Page 59

    ... MILLIMETERS MIN TYP MAX MIN 0.123 0.169 3.12 0.050 0.016 0.018 0.020 0.41 0.050 1.308 1.32 1.342 33.22 33.53 34.09 1.188 1.20 1.212 30.18 30.48 30.78 0.988 1.00 1.012 25.10 25.4 0.100 0.180 –59– ADSP-21xx INDEX PIN 5 ONLY 6 TOP VIEW ...

  • Page 60

    ... SYMBOL OUTLINE DIMENSIONS ADSP-2111 100-Lead Bumpered Plastic Quad Flatpack (PQFP Beveled Edge TOP VIEW (PINS DOWN NOTE: PIN 1 IS THE CENTER PIN ON THE BEVELED-EDGE SIDE OF THE PACKAGE. INCHES MIN TYP MAX MIN 0.180 0.020 0.030 0.040 0.508 0.130 0.140 0.150 3.302 ...

  • Page 61

    ... Part Number 1 ADSP-2101KG-66 ADSP-2101BG-66 ADSP-2101KP-66 ADSP-2101BP-66 ADSP-2101KS-66 ADSP-2101BS-66 ADSP-2101KG-80 ADSP-2101BG-80 ADSP-2101KP-80 ADSP-2101BP-80 ADSP-2101KS-80 ADSP-2101BS-80 ADSP-2101KP-100 ADSP-2101BP-100 ADSP-2101KS-100 ADSP-2101BS-100 ADSP-2101KG-100 ADSP-2101BG-100 ADSP-2101TG-50 ADSP-2103KP-40 (3.3 V) ADSP-2103BP-40 (3.3 V) ADSP-2103KS-40 (3.3 V) ADSP-2103BS-40 (3.3 V) ADSP-2105KP-55 ADSP-2105BP-55 ADSP-2105KP-80 ADSP-2105BP-80 ADSP-2115KP-66 ADSP-2115BP-66 ADSP-2115KS-66 ADSP-2115BS-66 ADSP-2115KST-66 ADSP-2115BST-66 ADSP-2115KP-80 ADSP-2115BP-80 ADSP-2115KS-80 ...

  • Page 62

    ... ADSP-21xx 1 Part Number ADSP-2111KG-52 ADSP-2111BG-52 ADSP-2111KS-52 ADSP-2111BS-52 ADSP-2111KG-66 ADSP-2111BG-66 ADSP-2111KS-66 ADSP-2111BS-66 ADSP-2111KG-80 ADSP-2111BG-80 ADSP-2111KS-80 ADSP-2111BS-80 ADSP-2111TG-52 2 ADSP-2161KP-66 2 ADSP-2161BP-66 2 ADSP-2161KS-66 2 ADSP-2161BS-66 2 ADSP-2162KP-40 (3 ADSP-2162BP-40 (3 ADSP-2162KS-40 (3 ADSP-2162BS-40 (3 ADSP-2163KP-66 2 ADSP-2163BP-66 2 ADSP-2163KS-66 2 ADSP-2163BS-66 2 ADSP-2163KP-100 2 ADSP-2163BP-100 2 ADSP-2163KS-100 2 ADSP-2163BS-100 2 ADSP-2164KP-40 (3 ADSP-2164BP-40 (3 ADSP-2164KS-40 (3 ADSP-2164BS-40 (3.3 V) NOTES Commercial Temperature Range ( +70 C). ...

  • Page 63

    –63– ...

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    –64– ...