ADSP-21062KS-160 Analog Devices Inc, ADSP-21062KS-160 Datasheet
ADSP-21062KS-160
Specifications of ADSP-21062KS-160
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ADSP-21062KS-160 Summary of contents
Page 1
... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a ...
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... OFF-CHIP MEMORY INTERFACING 4 gigawords addressable Programmable wait state generation, page-mode DRAM support DMA CONTROLLER 10 DMA channels for transfers between ADSP-2106x internal memory and external memory, external peripherals, host processor, serial ports, or link ports Background DMA transfers MHz, in parallel with full-speed processor execution Table 1 ...
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... See Ordering Guide.................................................. ADSP-21060/ADSP-21062 Specifications ..................... 15 Operating Conditions (5 V) ................................... 15 Electrical Characteristics (5 V) ................................ 15 Internal Power Dissipation (5 V) ............................. 16 External Power Dissipation (5 V) ............................ 17 ADSP-21060L/ADSP-21062L Specifications ................. 18 Operating Conditions (3.3 V) ................................. 18 Electrical Characteristics (3.3 V) ............................. 18 Internal Power Dissipation (3.3 V) .......................... 19 External Power Dissipation (3.3 V) .......................... 20 Absolute Maximum Ratings ................................... 20 ESD Caution ...
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... SRAM and integrated I/O periph- erals supported by a dedicated I/O bus. Fabricated in a high speed, low power CMOS process, the ADSP-2106x has instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. ...
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... The ADSP-21062/ADSP-21062L contains two megabits of on- chip SRAM, and the ADSP-21060/ADSP-21060L contains 4M bits of on-chip SRAM. The internal memory is organized as two equal sized blocks of 1M bit each for the ADSP-21062/ ADSP-21062L and two equal sized blocks of 2M bits each for the ADSP-21060/ADSP-21060L. Each can be configured for dif- ferent combinations of code and data storage ...
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... CLOCK ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 ADSP-2106x #3 ADDR31–0 CLKIN DATA47–0 RESET RPBA ID2–0 CONTROL 5 BR1–2, BR4–6 BR3 ADSP-2106x #2 ADDR31–0 CLKIN DATA47–0 RESET RPBA ID2–0 CONTROL CPA 5 BR1, BR3–6 BR2 ADSP-2106x #1 CLKIN ADDR31–0 ADDR RESET DATA47– ...
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... ADSP-2106x’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-2106xs and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock allows indivisible read-modify-write sequences for semaphores ...
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... Transfers are programmable as either transmit or receive. Program Booting The internal memory of the ADSP-2106x can be booted at sys- tem power-up from an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot source is controlled by the BMS (boot memory select), EBOOT (EPROM Boot), and LBOOT (link/host boot) pins ...
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... This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2106x architecture and functionality. For detailed information on the ADSP-21000 family core architecture and instruction set, refer to the ADSP-2106x SHARC User’s Manual, Revision 2.1. ...
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... WR is not later asserted (e.g conditional write instruction multiprocessing system output by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write asserted at the same time as the address output. A host processor using synchronous writes must assert this pin when writing to the ADSP-2106x(s) ...
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... DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to all ADSP-2106xs in the system. The CPA pin has an internal 5 k: pull-up resistor. If core access priority is not required in a system, the CPA pin should be left unconnected. ...
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... CLKIN I Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN. CLKIN should not be halted, changed, or operated below the minimum specified frequency. RESET I/A Processor Reset. Resets the ADSP-2106x to a known state and begins program execution at the program memory location specified by the hardware reset vector address ...
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... V . The TRST pin must be asserted (pulsed low) after power (through BTRST on the connector) or held low for proper operation of the ADSP-2106x. None of the Bxxx pins (Pins and 11) are connected on the EZ-ICE probe. The JTAG signals are terminated on the EZ-ICE probe as shown in Table 4 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC OTHER JTAG CONTROLLER Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems TDI EMU TCK TMS TRST TDO CLKIN ADSP-2106x #1 (OPTIONAL) TDI TDI TDO TDI EZ-ICE JTAG CONNECTOR TCK TMS EMU TRST TDO CLKIN OPTIONAL TDI TDO TDI TDO 5k * TDI ...
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... Applies to CPA pin. 8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k: during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL is not requesting bus mastership). 9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK. ...
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... Actual internal power DDINPEAK measurements made using typical applications are less than specified composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-2106x state during execution of IDLE instruction. DD Peak Activity (I ) High Activity (I DDINPEAK Multifunction Multifunction ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL POWER DISSIPATION (5 V) Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: ...
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... Applies to CPA pin. 8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k: during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL is not requesting bus mastership). 9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK. ...
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... Actual internal power DDINPEAK measurements made using typical applications are less than specified composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-2106xL state during execution of IDLE instruction. DD Peak Activity (I ) DDINPEAK Multifunction Cache 2 per Cycle (DM and PM) ...
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... Maximum P INT EXT u 10 MHz u 10 0.037 MHz u 10 0.000 MHz u 10 0.010 MHz u 10 0.026 MHz u 10 0.001 W ADSP-21060L/ADSP-21060LC ADSP-21062L 3.3 V –0 +4 0.5 V –0 +0 0.5 V –0 0 200 pF –65qC to +150qC 280qC 130qC ). The write . Select pins CK are different cannot INT P = 0.074 W ...
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... Assembly Lot Code n.n Silicon Revision yyww Date Code TIMING SPECIFICATIONS The ADSP-2106x processors are available at maximum proces- sor speeds of 33 MHz (–133), and 40 MHz (–160). The timing specifications are based on a CLKIN frequency of 40 MHz ns). The DT derating factor enables the calculation for CK ...
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... DD 2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-2106xs commu- nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset. CLKIN ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Interrupts Table 11. Interrupts Parameter Timing Requirements t IRQ2–0 Setup Before CLKIN High SIR t IRQ2–0 Hold Before CLKIN High HIR t IRQ2–0 Pulse Width IPW 1 Only required for IRQx recognition in the following cycle. 2 Applies only if t and t requirements are not met. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Flags Table 13. Flags Parameter Timing Requirements t FLAG3–0 IN Setup Before CLKIN High SFI t FLAG3–0 IN Hold After CLKIN High HFI t FLAG3–0 IN Delay After RD/WR Low DWRFI t FLAG3–0 IN Hold After RD/WR Deasserted HFIWR Switching Characteristics t FLAG3–0 OUT Delay After CLKIN High ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the Table 14. Memory Read—Bus Master Parameter Timing Requirements t Address Selects Delay to Data Valid DAD Low to Data Valid ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the Table 15. Memory Write—Bus Master Parameter Timing Requirements t ACK Delay from Address, Selects DAAK t ACK Delay from WR Low ...
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... Synchronous Read/Write—Bus Master Use these specifications for interfacing to external memory sys- tems that require CLKIN—relative timing or for accessing a slave ADSP-2106x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read— ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN t DADCCK ADDRCLK t DADRO ADDRESS, BMS, SW, MSx PAGE ACK (IN) READ CYCLE RD DATA (IN) WRITE CYCLE WR DATA (OUT) t ADRCK t t ADRCKH t DAAK t DPGC t DRWL t DRWL t SDDATO Figure 16. Synchronous Read/Write—Bus Master Rev Page March 2008 ADRCKL t HADRO t t HACK SACKC t DRDO t t HSDATI ...
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... Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI 2 For ADSP-21060C specification is –3.5 – 5DT/16 ns min 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min 7DT/16 ns max. 3 For ADSP-21062/ADSP-21062L/ADSP-21060C specification 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max. ...
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... For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN HBR HBG (OUT) BRx (OUT) CPA (OUT, O/D) HBG (I N) BRx, CPA (IN RPBA HBR REDY (O/D) REDY (A/D) HBG (OUT O PEN DRAIN, A/D = ACTIVE DRIVE Figure 18. Multiprocessor Bus Request and Host Bus Request Rev Page March 2008 t TRC ...
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... HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the HBGRCSV ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. 2 For ADSP-21060L, specification is 10.5 ns max; for ADSP-21060LC, specification is 12.5 ns max. 3 For ADSP-21060L/ADSP-21060LC, specification min, 8.5 ns max. Table 20. Write Cycle ...
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... WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 19. Synchronous REDY Timing ATR YPR SWR YWR L R DYP WR Figure 20. Asynchronous Read/Write—Host to ADSP-2106x Rev Page March 2008 ATWH TWH ...
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... Memory Interface Disable Before HBG Low MTRHBG t Memory Interface Enable After HBG High MENHBG 1 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min. 2 Strobes = RD, WR, PAGE, DMAG, BMS, SW. 3 For ADSP-21060LC, specification is 0.25 – DT/4 ns max addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN SBTS MEMORY INTERFACE DATA ACK ADRCLK Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion) t STSCK MIENA, MIENS, MIENHG t DATEN t ACKEN t ADCEN Rev Page March 2008 HTSCK MITRA, MITRS, MITRHG t DATTR t ACKTR t ADCTR ...
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... See Example System Hold Time Calculation on Page 47 5 For ADSP-21062/ADSP-21062L specification is –2.5 ns min max. 6 For ADSP-21060L/ADSP-21062L specification is –1 ns min. and DMAGx signals. For Paced Master mode, the data transfer is controlled by ADDR31–0, RD, WR, MS3–0, and ACK (not DMAG) ...
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... DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (OUT) (FROM ADSP-2106x TO EXTERNAL DEVICE) DATA (IN) (FROM EXTERNAL DEVICE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ADDR MSx, SW *MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER TIMING SPECIFICATIONS FOR ADDR31– ...
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... LACK goes low with t relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill. DLALC 3 For ADSP-21060C, specification DT/2 ns min DT/2 ns max. Table 24. Link Ports—Transmit Parameter Timing Requirements t LACK Setup Before LCLK High ...
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... LACK goes low with t relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill. DLALC 4 For ADSP-21060L, specification min max. For ADSP-21060C, specification min, 16.5 ns max. For ADSP-21060LC, specification min, 18.5 ns max Min Max ...
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... Min Max 19 –6. 2.25 2 –2.0 (t /4) – / /4) – 1. / max; for ADSP-21060C/ADSP-21062L, specification / max; for ADSP-21060C, specification Rev Page March 2008 3.3 V Min Max 19 –6.5 8 2.25 –2 (t /4) – 0.75 (t / /4) – 1 / /4) – min ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TRANSMIT CLKIN t DLCLK t t LCLKTWH LCLKTWL LCLK 1x OR LCLK 2x t DLDCH t HLDCH LDAT(3:0) OUT LACK (IN) t THE REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. SLACH RECEIVE CLKIN t LCLKRWH LCLK 1x OR LCLK 2x LDAT(3:0) t DLAHC LACK (OUT) ...
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... Referenced to sample edge. 2 RFS hold after RCK when MCE = 1, MFD = minimum from drive edge. TFS hold after TCK for late external TFS minimum from drive edge. 3 For ADSP-21060/ADSP-21060C/ADSP-21060LC, specification is 9.5 ns min. Table 29. Serial Ports—Internal Clock Parameter Timing Requirements t TFS Setup Before TCLK ...
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... Data Delay from Late External TFS or External RFS with MCE = 1, DDTLFSE 1, 2 MFD = 0 t Data Enable from Late FS or MCE = 1, MFD = 0 DDTENFS 1 MCE = 1, TFS enable and TFS valid follow t DDTLFSE 2 For ADSP-21062/ADSP-21062L, specification is 12.75 ns max; for ADSP-21060L/ADSP-21060LC, specification is 12.8 ns max. 3 For ADSP-21060/ADSP-21060C, specification min – min, 0. max. TSCLK SCLK ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t t SFSI HOFSE RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT— INTERNAL CLOCK DRIVE EDGE t SCLKIW TCLK t DFSI ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC RCLK RFS DT TCLK TFS DT EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE HDTE/I DDTENFS 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I TDDTENFS t HDTE/I 1ST BIT t DDTLFSE Figure 26. Serial Ports—External Late Frame Sync Rev ...
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... TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. 2 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is 18.5 ns min. 3 System Outputs = DATA63–0, ADDR31–0, MS3–0, RD, WR, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7– ...
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... V OL (MEASURED) Output Drive Characteristics OUTPUT STARTS DRIVING Figure 31 ers of the ADSP-2106x. The curves represent the current drive capability of the output drivers as a function of output voltage. Rev Page March 2008 (Figure using the equation given above. Choose 'V DECAY is the total bus capacitance (per data ...
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... SOURCE VOLTAGE - V Figure 31. ADSP-21062 Typical Output Drive Currents (V 16.0 14.0 12.0 RISE TIME 10 0.005x + 3.7 8.0 FALL TIME 6.0 4.0 2 0.0031x + 1 100 ...
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... 3.0V, +85°C 3.3V, +25° 100 OL - 120 0.5 1.0 1.5 2.0 Figure 35. ADSP-21062 Typical Output Drive Currents ( 0.0329x - 1. NOMINAL - 100 125 LOAD CAPACITANCE - pF Figure 36. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature 3.6V, - 40°C 3.6V, - 40°C 2.5 3 ...
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... Operating Con- age versions, one with a copper/tungsten heat slug on top of the package (CZ) for air cooling, and one with the heat slug on the bottom (CW) for cooling through the board. The ADSP-2106x is specified for a case temperature (T T data sheet specification is not exceeded, a heatsink and/or CASE an air flow source may be used ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 225-BALL PBGA BALL CONFIGURATIONS Table 40. ADSP-2106x 225-Ball Metric PBGA Ball Assignments (B-225-2) Pin PBGA Pin Name Pin Number Name BMS A01 ADDR25 ADDR30 A02 ADDR26 DMAR2 A03 MS2 DT1 A04 ADDR29 RCLK1 A05 DMAR1 TCLK0 A06 TFS1 RCLK0 A07 CPA ...
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... DATA8 DATA10 DATA9 DATA7 DATA4 DATA6 DATA5 DATA2 L0DAT0 DATA3 DATA1 L0DAT3 L1DAT3 DATA0 L0DAT1 L0ACK L1DAT0 L0DAT2 L0CLK L1DAT2 L1CLK Figure 39. ADSP-21060/ADSP-21062 BGA Pin Assignments (Top View, Summary PAGE CLKIN ADRCLK RCLK0 TCLK0 BR6 RD ACK REDY DR0 BR4 DMAG1 WR RFS0 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 240-LEAD MQFP_PQ4/CQFP PIN CONFIGURATIONS Table 41. ADSP-2106x MQFP_PQ4, ADSP-21060CW, and ADSP-21060LCW CQFP Pin Assignments (SP-240-2, QS-240-2) Pin Name Pin No. Pin Name Pin No. TDI 1 ADDR20 41 TRST 2 ADDR21 GND 43 DD TDO 4 ADDR22 44 TIMEXP 5 ADDR23 45 EMU 6 ADDR24 46 ICSA FLAG3 8 GND 48 FLAG2 FLAG1 10 ADDR25 50 FLAG0 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 42. ADSP-21060CZ/21060LCZ CQFP Pin Assignments (QS-240-1) Pin Name Pin No. Pin Name Pin No. GND 1 DATA29 41 DATA0 2 GND 42 DATA1 3 DATA30 43 DATA2 4 DATA31 DATA32 45 DD DATA3 6 GND 46 DATA4 DATA5 GND 9 DATA33 49 DATA6 10 DATA34 50 DATA7 11 DATA35 51 DATA8 GND 53 DD DATA9 14 DATA36 54 DATA10 15 DATA37 55 DATA11 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC OUTLINE DIMENSIONS 2.70 MAX 23.20 23.00 SQ 22.80 BALL A1 INDICATOR 18.00 20.10 BSC SQ 20.00 SQ TOP VIEW 19.90 1.27 BSC 0. PLACES DETAIL A 0.70 0.60 0.50 SEATING PLANE BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MS-034-AAJ-2 Figure 40. 225-Ball Plastic Ball Grid Array [PBGA] (B-225-2) Dimensions shown in millimeters Rev ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 0.66 0.56 0.46 SEATING PLANE 3.50 3.40 0.20 3.30 0.09 0.38 7° 0.25 0° 0.076 COPLANARITY VIEW A ROTATED 90° CCW Figure 41. 240-Lead Metric Quad Flat Package, Thermally Enhanced “PowerQuad” [MQFP_PQ4] 34.60 BSC SQ 29.50 REF 4.10 3.78 3.55 240 1 PIN 1 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 32.00 BSC SQ PIN 1 240 INDICATOR 1 TOP VIEW (PINS DOWN) HEAT SLUG 60 61 19.00 REF SQ 4.30 3.62 2.95 7° 0.90 0.23 -3° 0.75 0.20 0.60 0.17 NOTES: 1. LEAD FINISH = GOLD PLATE 2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX (Sweep and/or Offset can be used as the controlling dimension). ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 75.00 BSC SQ 29.50 BSC 2.05 120 121 65.90 BSC TOP VIEW HEAT SLUG 180 181 75.50 BSC SQ 0.50 3.42 SIDE VIEW 3.17 2.92 Figure 43. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Down [CQFP] 2.60 2.55 2.50 3.60 3.55 3.50 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 32.00 BSC SQ PIN 1 240 INDICATOR 1 SEAL RING LID TOP VIEW (PINS DOWN 28.05 27.80 SQ 27.55 4.20 3.52 2.85 7° 0.90 0.23 -3° 0.75 0.20 0.60 0.17 NOTES: 1. LEAD FINISH = GOLD PLATE 2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX (Sweep and/or Offset can be used as the controlling dimension). ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 75.00 BSC SQ 29.50 BSC 2.05 120 121 SEAL RING LID 65.90 BSC TOP VIEW 180 181 75.50 BSC SQ 0.50 3.42 SIDE VIEW 3.17 2.92 Figure 45. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Up [CQFP] SURFACE-MOUNT DESIGN Table 43 is provided as an aide to PCB design. For industry- ...
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... MHz 1 ASDP-21060LCW-133 –40qC to +100qC 33 MHz 1 ASDP-21060LCW-160 –40qC to +100qC 40 MHz 1, 2 ASDP-21060LCWZ-160 –40qC to +100qC 40 MHz ADSP-21062KS-133 0qC to 85qC 2 ADSP-21062KSZ-133 0qC to 85qC ADSP-21062KS-160 0qC to 85qC 2 ADSP-21062KSZ-160 0qC to 85qC ADSP-21062KB-160 0qC to 85qC 2 ADSP-21062KBZ-160 0qC to 85qC ADSP-21062CS-160 –40qC to +100qC 40 MHz 2 ADSP-21062CSZ-160 –40qC to +100qC 40 MHz ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev Page March 2008 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev Page March 2008 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00167-0-3/08(F) Rev Page March 2008 ...