ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 15

ADSP-21065L 60 Mhz

ADSP-21065LCSZ-240

Manufacturer Part Number
ADSP-21065LCSZ-240
Description
ADSP-21065L 60 Mhz
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21065LCSZ-240

Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
60MHz
Mips
60
Device Input Clock Speed
60MHz
Ram Size
68KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADS-P21065LCSZ240
ADS-P21065LCSZ240

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
AD
Quantity:
310
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Parameter
Timer
Timing Requirements:
t
t
Switching Characteristics:
t
t
Parameter
Flags
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
NOTE
1
REV. C
Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
STI
HTI
DTEX
HTEX
SFI
HFI
DFO
HFO
DFOE
DFOD
FLAG
FLAG
11–0
11–0
SDCLK
SDCLK
OUT
IN
Timer Setup Before SDCLK High
Timer Hold After SDCLK High
Timer Delay After SDCLK High
Timer Hold After SDCLK High
FLAG
FLAG
FLAG
FLAG
SDCLK High to FLAG
SDCLK High to FLAG
11-0
11-0
11-0
11-0
t
DFOE
IN Setup Before SDCLK High
IN Hold After SDCLK High
OUT Delay After SDCLK High
OUT Hold After SDCLK High
IRQ 2-0
CLKIN
11-0
11-0
t
OUT Enable
OUT Disable
SFI
t
HFI
1
t
DFO
Figure 9. Interrupts
1
Figure 10. Flags
t
IPW
FLAG OUTPUT
–15–
t
SIR
t
t
HIR
HFO
t
DFO
Min
0.0
6.0
–5.0
Min
–2.0
6.0
–4.0
–4.0
t
DFOD
ADSP-21065L
Max
1.0
Max
1.0
–1.75
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns

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