ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 24

• Manufacturer Part Number: ADSP-21065LCSZ-240
• Description: ADSP-21065L 60 Mhz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LCSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADS-P21065LCSZ240; ADS-P21065LCSZ240

ADSP-21065L
Asynchronous Read/Write—Host to ADSP-21065L
Use these specifications for asynchronous host processor accesses of an ADSP-21065L, after the host has asserted CS and HBR
(low). After the ADSP-21065L returns HBG, the host can drive the RD and WR pins to access the ADSP-21065L’s IOP registers.
HBR and HBG are assumed low for this timing. Writes can occur at a minimum interval of (1/2) t
Parameter
Read Cycle
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
Write Cycle
Timing Requirements:
t
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
NOTE
*Not required if RD and address are valid t
SADRDL
HADRDH
WRWH
DRDHRDY
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
HDARWH
SCSWRL
HCSWRH
SADWRH
HADWRH
WWRL
WRWH
DWRHRDY
SDATWH
HDATWH
DRDYWRL
RDYPWR
face, in the ADSP-21065L SHARC User’s Manual, Second Edition.
RD or WR goes low or by t
Address Setup
Address Hold/CS Hold Low After RD High
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
CS Low Setup Before WR Low
CS Low Hold After WR High
Address Setup Before WR High
Address Hold After WR High
WR Low Width
RD/WR High Width
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
Data Hold After WR High
REDY (O/D) or (A/D) Low Delay After WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See Host Inter-
/
CS Low Before RD Low*
HBGRCSV
after HBG goes low. For first access after HBR asserted, ADDR23-0 must be a nonMMS value 1/2 t
–24–
Min
0.0
0.0
6.0
0.0
0.0
1.5
28.0 + DT
2.0
0.0
0.0
5.0
2.0
7.0
6.0
0.0
5.0
1.0
7.75
CK
.
Max
13.5
10.0
13.5
CLK
before
REV. C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns