ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 28

ADSP-21065L 60 Mhz

ADSP-21065LCSZ-240

Manufacturer Part Number
ADSP-21065LCSZ-240
Description
ADSP-21065L 60 Mhz
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21065LCSZ-240

Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
60MHz
Mips
60
Device Input Clock Speed
60MHz
Ram Size
68KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADS-P21065LCSZ240
ADS-P21065LCSZ240

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
AD
Quantity:
310
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21065L
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled
by the ADDR
Paced Master mode, the data transfer is controlled by ADDR
the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR
Parameter
Timing Requirements:
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) ¥ t
HI = t
NOTES
1
2
3
4
Only required for recognition in the current cycle.
t
t
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
SDRLC
SDRHC
WDR
SDATDGL
HDATIDG
DATDRH
DMARLL
DMARH
DDGL
WDGH
WDGL
HDGC
DADGH
DDGHA
VDATDGH
DATRDGH
DGWRL
DGWRH
DGWRR
DGRDL
DRDGH
DGRDR
DGWR
data can be driven t
equals the number of extra cycles that the access is prolonged.
SDATDGL
VDATDGH
CK
23-0
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
, RD, WR, MS
23-0
DATDRH
, RD, WR, SW, MS
DMARx Low Setup Before CLKIN
DMARx High Setup Before CLKIN
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low
Data Hold After DMAGx High
Data Valid After DMARx High
DMARx Low Edge to Low Edge
DMARx Width High
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay After CLKIN
Address Select Valid to DMAGx High
Address Select Hold After DMAGx High
Data Valid Before DMAGx High
Data Disable After DMAGx High
WR Low Before DMAGx Low
DMAGx Low Before WR High
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
RD High Before DMAGx High
DMAGx High to WR, RD Low
after DMARx is brought high.
3-0
, SW, DATA
3-0
, ACK, and DMAG signals. External mode cannot be used for transfers with SDRAM. For
31-0
, and ACK also apply.
CK
.
2
2
3
4
1
1
23-0
–28–
, RD, WR, MS
Min
5.0
5.0
6.0
0.0
18.0 + 14 DT
6.0
14.0 + 10 DT
10.0 + 12 DT + HI
16.0 + 20 DT
0.0 – 2 DT
28.0 + 16 DT
–1.0
16.0 + 20 DT
0.0
5.0 + 6 DT
18.0 + 19 DT + W
0.75 + 1 DT
5.0
24.0 + 26 DT + W
0.0
5.0 + 6 DT + HI
3-0
, and ACK (not DMAG). For Paced Master mode,
VDATDGH
Max
15.0 + 20 DT
25.0 + 14 DT
20.0 + 10 DT
6.0 – 2 DT
4.0
8.0 + 6 DT
3.0 + 1 DT
8.0
2.0
= 8 + 9 DT + (n ¥ t
CK
) where n
REV. C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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