ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 3

• Manufacturer Part Number: ADSP-21065LCSZ-240
• Description: ADSP-21065L 60 Mhz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LCSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADS-P21065LCSZ240; ADS-P21065LCSZ240

GENERAL DESCRIPTION
The ADSP-21065L is a powerful member of the SHARC
family of 32-bit processors optimized for cost sensitive appli-
cations. The SHARC—Super Harvard Architecture—offers the
highest levels of performance and memory integration of any
32-bit DSP in the industry—they are also the only DSP in the
industry that offer both fixed and floating-point capabilities,
without compromising precision or performance.
The ADSP-21065L is fabricated in a high speed, low power
CMOS process, 0.35 mm technology. With its on-chip instruc-
tion cache, the processor can execute every instruction in a
single cycle. Table I lists the performance benchmarks for the
ADSP-21065L.
The ADSP-21065L SHARC combines a floating-point DSP
core with integrated, on-chip system features, including a
544 Kbit SRAM memory, host processor interface, DMA con-
troller, SDRAM controller, and enhanced serial ports.
Figure 1 shows a block diagram of the ADSP-21065L, illustrat-
ing the following architectural features:
Benchmark
Cycle Time
1024-Pt. Complex FFT
Matrix Multiply (Pipelined)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide Y/X
Inverse Square Root (1/÷x)
DMA Transfers
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-21065L is code and function compatible with the
ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L
includes the following architectural features of the SHARC
family core.
REV. C
Computation Units (ALU, Multiplier, and Shifter) with a
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Timers with Event Capture Modes
On-Chip, dual-ported SRAM
External Port for Interfacing to Off-Chip Memory and
Host Port and SDRAM Interface
DMA Controller
Enhanced Serial Ports
JTAG Test Access Port
(Radix 4, with Digit Reverse)
[3 ¥ 3] ¥ [3 ¥ 1]
[4 ¥ 4] ¥ [4 ¥ 1]
Shared Data Register File
Peripherals
Table I. Performance Benchmarks
Timing
15.00 ns
135 ns
240 ns
15 ns
60 ns
90 ns
135 ns
264 Mbytes/sec.
0.274 ns
Cycles
1
18221
9
16
1
4
6
9
–3–
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all
perform single-cycle instructions. The three units are arranged
in parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier
operations. These computation units support IEEE 32-bit
single-precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21065L features an enhanced Super Harvard Archi-
tecture in which the data memory (DM) bus transfers data and
the program memory (PM) bus transfers both instructions and
data (see Figure 1). With its separate program and data memory
buses, and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction Cache
The ADSP-21065L includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions that
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21065L’s two data address generators (DAGs)
implement circular data buffers in hardware. Circular buffers
allow efficient programming of delay lines and other data
CLOCK
RESET
01
Figure 2. ADSP-21065L Single-Processor System
CONTROL
SPORT0
TX0_A
TX0_B
RX0_A
RX0_B
SPORT1
TX1_A
TX1_B
RX1_A
RX1_B
CLKIN
RESET
ID
ADSP-21065L
1-0
#1
SDCLK
ADDR
DATA
SDCKE
SDA10
SDWE
MS
SBTS
REDY
BMS
DQM
ACK
HBG
HBR
RAS
CAS
CPA
BR
BR
WR
SW
31-0
RD
23-0
CS
3-0
1-0
2
1
ADSP-21065L
CS
ADDR
DATA
ADDR
CS
DATA
CS
ADDR
DATA
RAS
CAS
DQM
WE
CLK
CKE
A10
PROCESSOR
(OPTIONAL)
(OPTIONAL)
HOST
(OPTIONAL)
SDRAM
EPROM
BOOT