ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 9

ADSP-21065L 60 Mhz

ADSP-21065LCSZ-240

Manufacturer Part Number
ADSP-21065LCSZ-240
Description
ADSP-21065L 60 Mhz
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21065LCSZ-240

Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
60MHz
Mips
60
Device Input Clock Speed
60MHz
Ram Size
68KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADS-P21065LCSZ240
ADS-P21065LCSZ240

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
AD
Quantity:
310
Part Number:
ADSP-21065LCSZ-240
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Pin
BMS
CLKIN
RESET
TCK
TMS
TDI
TDO
TRST
EMU (O/D)
BMSTR
CAS
RAS
SDWE
DQM
SDCLK
SDCKE
REV. C
1-0
Type
I/O/T*
I
I/A
I
I/S
I/S
O
I/A
O
O
I/O/T
I/O/T
I/O/T
O/T
I/O/S/T
I/O/T
Function
Boot Memory Select. Output: used as chip select for boot EPROM devices (when BSEL = 1).
In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that
no booting will occur and that the ADSP-21065L will begin executing instructions from exter-
nal memory. See following table. This input is a system configuration selection which should be
hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
BSEL
1
0
0
Clock In. Used in conjunction with XTAL, configures the ADSP-21065L to use either its
internal clock generator or an external clock source. The external crystal should be rated at 1x
frequency.
Connecting the necessary components to CLKIN and XTAL enables the internal clock genera-
tor. The ADSP-21065L’s internal clock generator multiplies the 1x clock to generate 2x clock
for its core and SDRAM. It drives 2x clock out on the SDCLKx pins for the SDRAM interface
to use. See also SDCLKx.
Connecting the 1x external clock to CLKIN while leaving XTAL unconnected configures the
ADSP-21065L to use the external clock source. The instruction cycle rate is equal to 2x CLKIN.
CLKIN may not be halted, changed, or operated below the specified frequency.
Processor Reset. Resets the ADSP-21065L to a known state and begins execution at the
program memory location specified by the hardware reset vector address. This input must be
asserted at power-up.
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kW internal
pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kW
internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-21065L. TRST has a 20 kW internal
pull-up resistor.
Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target board connector
only.
Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21065L is cur-
rent bus master of the shared external bus. The ADSP-21065L drives BMSTR high only while
it is the bus master. In a single-processor system (ID = 00), the processor drives this pin high.
SDRAM Column Access Strobe. Provides the column address. In conjunction with RAS,
MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Row Access Strobe. Provides the row address. In conjunction with CAS, MSx,
SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes
SDA10, defines the operation for the SDRAM to perform.
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used to block write
operations.
SDRAM 2x Clock Output. In systems with multiple SDRAM devices connected in parallel,
supports the corresponding increased clock load requirements, eliminating need of off-chip
clock buffers. Either SDCLK
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet
supplied with your SDRAM device.
BMS
Output
1 (Input)
0 (Input)
Booting Mode
EPROM (connect BMS to EPROM chip select).
Host processor (HBW [SYSCON] bit selects host bus width).
No booting. Processor executes from external memory.
–9–
1
or both SDCLKx pins can be three-stated.
ADSP-21065L

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