ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet

IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC

ADSP-21160NCB-100

Manufacturer Part Number
ADSP-21160NCB-100
Description
IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr

Specifications of ADSP-21160NCB-100

Rohs Status
RoHS non-compliant
Interface
Host Interface, Link Port, Serial Port
Clock Rate
100MHz
Non-volatile Memory
External
On-chip Ram
512kB
Voltage - I/o
3.30V
Voltage - Core
1.90V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
400-BGA
Package
400BGA
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
100 MHz
Ram Size
512 KB
Device Million Instructions Per Second
100 MIPS
Lead Free Status / RoHS Status

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21160NCB-100
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21160NCB-100
Manufacturer:
ADI
Quantity:
2 186
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
a
SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Super Harvard Architecture—Four Independent Buses
Backwards Compatible—Assembly Source Level
Single-Instruction-Multiple-Data (SIMD) Computational
Medical, Military, Graphics, Imaging, and
Communication
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Compatible with Code for ADSP-2106x DSPs
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
8
DAG1
CONNECT
4
MULT
BUS
(PX)
32
8
16
REGISTER
DAG2
4
DATA
CORE PROCESSOR
(PEX)
FILE
DM ADDRESS BUS
40-BIT
PM ADDRESS BUS
32
PM DATA BUS
DM DATA BUS
TIMER
BARREL
SHIFTER
ALU
SEQUENCER
PROGRAM
INSTRUCTION
32
CACHE
16/32/40/48/64
32/40/64
48-BIT
32
32
FUNCTIONAL BLOCK DIAGRAM
SHIFTER
BARREL
ALU
ADDR
16
PROCESSOR PORT
REGISTER
ADDR
(PEY)
DATA
FILE
40-BIT
DUAL-PORTED BLOCKS
TWO INDEPENDENT
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
DATA
Integrated Peripherals—Integrated I/O Processor,
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Dual Data Address Generators (DAGs) with Modulo and
Zero-Overhead Looping and Single-Cycle Loop Setup,
DUAL-PORTED SRAM
4 M Bits On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
Operations in Both Computational Units
Bit-Reverse Addressing
Providing Efficient Program Sequencing
MULT
DATA
DATA
DATA
I/O PORT
IOD
64
DATA BUFFERS
ADDR
STATUS AND
REGISTERS
CONTROL,
(MEMORY
MAPPED)
DSP Microcomputer
© 2003 Analog Devices, Inc. All rights reserved.
IOP
ADDR
IOA
18
I/O PROCESSOR
ADSP-21160N
MULTIPROCESSOR
SERIAL PORTS
CONTROLLER
LINK PORTS
HOST PORT
INTERFACE
ADDR BUS
DATA BUS
EXTERNAL
DMA
(2)
(6)
MUX
MUX
PORT
EMULATION
TEST AND
JTAG
S
www.analog.com
32
64
6
60
4
6
6

Related parts for ADSP-21160NCB-100

ADSP-21160NCB-100 Summary of contents

Page 1

... Super Harvard Architecture—Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive, Zero-Overhead I/O Backwards Compatible—Assembly Source Level Compatible with Code for ADSP-2106x DSPs Single-Instruction-Multiple-Data (SIMD) Computational Architecture—Two 32-Bit IEEE Floating-Point Computation Units, Each with a Multiplier, ALU, ...

Page 2

... Multiprocessing Support Provides: Glueless Connection for Scalable DSP Multiprocessing Architecture Distributed On-Chip Bus Arbitration for Parallel Bus Connect Six ADSP-21160Ns Plus Host Six Link Ports for Point-to-Point Connectivity and Array Multiprocessing Serial Ports Provide: Two 50M Bits/s Synchronous Serial Ports with ...

Page 3

... Memory Write—Bus Master . . . . . . . . . . . . . . . . 22 Synchronous Read/Write—Bus Master . . . . . . . . 23 Synchronous Read/Write—Bus Slave . . . . . . . . . 25 Multiprocessor Bus Request and Host Bus Request . . . . . . . . . . . . . . . . . . . . . . 26 Asynchronous Read/Write—Host to ADSP-21160N . . . . . . . . . . . . . . . . . . . . . . 28 Three-State Timing—Bus Master, Bus Slave . . . . 30 DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . 32 Link Ports —Receive, Transmit . . . . . . . . . . . . . . 34 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 JTAG Test Access Port and Emulation . . . . . . . . 39 Output Drive Currents ...

Page 4

... ADSP-2106x on a range of DSP algorithms. Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21160N has instruction cycle time. With its SIMD computational hardware running at 100 MHz, the ADSP-21160N can perform 600 million math operations per second ...

Page 5

... I/O proces- sor single cycle. On the ADSP-21160N, the memory can be configured as a maximum of 128K words of 32-bit data, 256K words of 16-bit data, 85K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits ...

Page 6

... ADSP- 21160N’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems con- taining up to six ADSP-21160Ns and a host processor. Master processor changeover incurs only one cycle of overhead. Bus 0xFFFF FFFF arbitration is selectable as either fixed or rotating priority ...

Page 7

... Maximum throughput for interprocessor data transfer is 400M bytes/s over the external port. Broadcast writes allow simultaneous transmission of data to all ADSP-21160Ns and can be used to implement reflective semaphores. CLKIN RESET RPBA 3 ID2–0 011 CLKIN RESET RPBA 3 ID2–0 010 CLKIN RESET ...

Page 8

... Boot), and LBOOT (Link/Host Boot) pins. 32-bit and 16-bit host processors can be used for booting. Phase-Locked Loop The ADSP-21160N uses an on-chip PLL to generate the internal clock for the core. Ratios of 2:1, 3:1, and 4:1 between the core and CLKIN are supported. The CLK_CFG pins are used to select the ratio ...

Page 9

... This document is updated regularly to keep pace with improvements to emulator support. Additional Information This data sheet provides a general overview of the ADSP-21160N architecture and functionality. For detailed information on the ADSP-2116x family core architecture and instruction set, refer to the ADSP-21160 SHARC DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference ...

Page 10

... MS3–0 outputs transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. MS3–0 has internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x. RDL Memory Read Low Strobe ...

Page 11

... TCOUNT decrements to zero. HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the ADSP- 21160N’s external bus. When HBR is asserted in a multiprocessing system, the ADSP- 21160N that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21160N places the address, data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21160N bus requests (BR6– ...

Page 12

... Priority Access. Asserting its PA pin allows an ADSP-21160N bus slave to interrupt I/O/T background DMA transfers and gain access to the external bus connected to all ADSP-21160Ns in the system. If access priority is not required in a system, the PA pin should be left unconnected. PA has internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x. ...

Page 13

... O/T Core Instruction Fetch. Signal is active low when an external instruction fetch is performed. Driven by bus master only. Three-state when host is bus master. CIF has internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x Core Power Supply. Nominally 1 and supplies the DSP’s core processor DDINT (40 pins) ...

Page 14

... ADSP-21160N SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Internal (Core) Supply Voltage DDINT AV Analog (PLL) Supply Voltage DD V External (I/O) Supply Voltage DDEXT T Case Operating Temperature CASE V High Level Input Voltage, IH1 V High Level Input Voltage, IH2 V Low Level Input Voltage, IL Specifications subject to change without notice. ...

Page 15

... DD-INHIGH composite average based on a range of low activity code. For more information, see Power Dissipation DD-INLOW 18 Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see Power Dissipation 19 Applies to all signal pins. 20 Guaranteed, but not tested. ABSOLUTE MAXIMUM RATINGS ...

Page 16

... Figure 7). The bootstrap Schottky diode connected between the 1.9 V and 3.3 V power supplies protects the ADSP-21160N from partially powering the 3.3 V supply. Including a Schottky diode will shorten the delay between the supply ramps and thus prevent damage to the ESD diode protection circuitry. With this technique, if the 1 ...

Page 17

... If setup time is not met, one additional CLKIN cycle may SRST t IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 6. Power-up Sequencing 3.3V I/O VOLTAGE REGULATOR 1.9V CORE VOLTAGE REGULATOR Figure 7. Dual Voltage Schottky Diode –17– ADSP-21160N Min Max 0 – 50 +200 0 200 4096t CK t CORERST V DDEXT ADSP-21160 V DDINT Unit µs µs ms ...

Page 18

... CLKIN (not including start-up time of external clock oscillator Only required if multiple ADSP-21160Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21160Ns communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset. ...

Page 19

... HIR CLKIN IRQ2–0 Timer For Timer, see Table 8 and Figure 11. Table 8. Timer Parameter Switching Characteristic t CLKIN High to TIMEXP DTEX CLKIN t DTEX TIMEXP REV SIR t IPW Figure 10. Interrupts Figure 11. Timer –19– ADSP-21160N Min Max Unit 2 HIR Min Max Unit DTEX ...

Page 20

... ADSP-21160N Flags For Flags, see Table 9 and Figure 12. Table 9. Flags Parameter Timing Requirements t FLAG3–0 IN Setup Before CLKIN High SFI t FLAG3–0 IN Hold After CLKIN High HFI FLAG3–0 IN Delay After RDx/WRx Low t DWRFI FLAG3–0 IN Hold After RDx/WRx Deasserted t HFIWR ...

Page 21

... DARL RDx DATA ACK CLKIN WRx DMAGx REV. 0 apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing parameters only applies to asynchronous access mode. Min ...

Page 22

... WD E DATA t DAA K ACK CLKIN RDx DMAGx apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing parameters only applies to asynchronous access mode. Min 0.5t ...

Page 23

... Figure 15. Use these specifications for inter- facing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-21160N (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read–Bus Master Table 12. Synchronous Read/Write— ...

Page 24

... ADSP-21160N CLKIN t DCKOO CLKOUT t DADDO ADDRESS MSx, BRST, CIF PAGE ACK (IN) ACK (OUT) READ CYCLE RDx DATA (IN) WRITE CYCLE WRx DATA (OUT) Figure 15. Synchronous Read/Write—Bus Master t CKOP t t CKWH t DPGO t SACKC t t DACKMO ACKMTR t DRWL t DRWL t DDATO –24– CKWL ...

Page 25

... Synchronous Read/Write—Bus Slave See Table 13 and Figure 16. Use these specifications for ADSP- 21160N bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements. Table 13. Synchronous Read/Write—Bus Slave ...

Page 26

... Multiprocessor Bus Request and Host Bus Request See Table 14 and Figure 17. Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ns (BRx host processor, both synchronous and asynchronous (HBR, HBG). Table 14. Multiprocessor Bus Request and Host Bus Request Parameter Timing Requirements ...

Page 27

... O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 17. Multiprocessor Bus Request and Host Bus Request REV HHBRI t DHBGO t HHBGO t DBRO t HBRO t DPASO t DPAMO t SRP BAI t HRPBAI t T RDY HG t HBGRCSV –27– ADSP-21160N t TRP AS t PATR t S HBG I t HHBG I t SBRI t HBRI t ARDY TR ...

Page 28

... REDY (O/D) or (A/D) Low Delay After WRx/CS Low t DRDYWRL t REDY (O/D) or (A/D) Low Pulsewidth for Write RDYPWR After HBG is returned by the ADSP-21160N, the host can drive the RDx and WRx pins to access the ADSP-21160N’s internal 16, Figure 18, and memory or IOP registers. HBR and HBG are assumed low for this timing. – ...

Page 29

... READ CYCLE ADDRESS/ CS RDx D ATA (OUT) REDY (O/ D) REDY (A/D) Figure 18. Asynchronous Read—Host to ADSP-21160N WRITE CYCLE ADDRESS CS WRx DATA (I N) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN ACTIVE DRIVE Figure 19. Asynchronous Write—Host to ADSP-21160N REV YRD SWR L t WWR TWH ...

Page 30

... ADSP-21160N Three-State Timing—Bus Master, Bus Slave See Table 17 and Figure 20. These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host tran- sition cycles (HTC) as well as the SBTS pin. Table 17. Three-State Timing— ...

Page 31

... HBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RDx, WRx, MSx, PAGE, DMAGx. BMS (IN EPROM BOOT MODE) Figure 20. Three-State Timing—Bus Master, Bus Slave REV STSCK t HTSCK t t MIENHG MITRA, MITRS, t DATTR t ACKTR t CDCTR t MENHBG –31– ADSP-21160N t MITRHG t ATRHBG t STRHBG t PTRHBG t BTRHBG ...

Page 32

... ADSP-21160N DMA Handshake See Table 18 and Figure 21. These specifications describe the three DMA handshake modes. In all three modes, DMARx is used to initiate transfers. For handshake mode, DMAGx controls the latching or enabling of data externally. For external hand- shake mode, the data transfer is controlled by the ADDR31–0, RDx, WRx, PAGE, MS3– ...

Page 33

... DMAGx TRANSFERS BETWEEN ADSP-2116X INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2116X TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-2116X) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTER NAL MEMORY*(EXTERNAL HANDSHAKE MODE) WRx (EXTERNAL DEVICE TO EXTERNAL MEMORY) RDx (EXTERNAL MEMOR Y TO EXTERNAL DEVICE) ...

Page 34

... ADSP-21160N Link Ports —Receive, Transmit For Link Ports, see Table 19, Table 20, Figure 23. Calculation of link receiver data setup and hold, relative to link clock, is required to determine the maximum allowable skew that can be introduced in the transmission path, between LDATA and LCLK. Setup skew is the maximum delay ...

Page 35

... DLDCH t HLDCH LDAT(7:0) OUT LACK (IN) t THE REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. SLACH REV. 0 LAST NIBBLE/BYTE FIRST NIBBLE/BYTE TRANSMITTED TRANSMITTED t t SLACH HLACH Figure 23. Link Ports—Transmit –35– ADSP-21160N LCLK INACTIVE (HIGH) t DLACLK ...

Page 36

... ADSP-21160N Serial Ports For Serial Ports, see Table 21, Table 22, Table 25, Table 26, Table 27, Figure 24, and determine whether communication is possible between two Table 21. Serial Ports—External Clock Parameter Timing Requirements t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK ...

Page 37

... HDTE/I DDTENFS 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I TDDTENFS t HDTE/I 1ST BIT 2ND BIT t DDTLFSE –37– ADSP-21160N Min Max 4.5 –1.5 7.5 0 0.5t –1.5 0.5t +1.5 SCLK SCLK Min Max 13 1.0 2ND BIT Unit ...

Page 38

... ADSP-21160N DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t t SFSI HOFSE RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT— INTERNAL CLOCK DRIVE EDGE t SCLKIW TCLK t DFSI ...

Page 39

... FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS. TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS Figure 26. JTAG Test Access Port and Emulation REV. 0 Table 28 and TCK t t STAP HTAP t DTDO t t DSYS –39– ADSP-21160N Min Max SSYS HSYS Unit ...

Page 40

... ADSP-21160N Output Drive Currents Figure 27 shows typical I–V characteristics for the output drivers of the ADSP-21160N. The curves represent the current drive capability of the output drivers as a function of output voltage 3.47V, –45°C DDEXT V = 3.3V, 25°C 60 DDEXT 3.11V, 115°C DDEXT 3.11V, 115°C DDEXT – ...

Page 41

... Data 64 50 CLKOUT 1 Test Conditions The test conditions for timing parameters appearing in ADSP- 21160N specifications on Page 14 include output disable time, output enable time, and capacitive loading. Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage ...

Page 42

... Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature) Environmental Conditions The ADSP-21160NKB-100 and ADSP-21160NCB-100 are provided in a 400-Ball Metric PBGA (Plastic Ball Grid Array) package. Thermal Characteristics 200 250 The ADSP-21160N is specified for a case temperature (T To ensure that the T a heatsink and/or an air flow source may be used ...

Page 43

... F20 L2CLK G20 CLKIN L01 K02 CLK_CFG_1 L02 K03 AGND L03 K04 CLK_CFG_2 L04 K05 V L05 DDEXT K06 V L06 DDINT –43– ADSP-21160N Pin Name Pin No. DATA[28] D01 DATA[25] D02 DATA[20] D03 DATA[19] D04 DATA[12] D05 V D06 DDEXT V D07 DDINT V D08 ...

Page 44

... ADSP-21160N Table 32. 400-Ball Metric PBGA Pin Assignments (continued) Pin Name Pin No. Pin Name GND J07 GND GND J08 GND GND J09 GND GND J10 GND GND J11 GND GND J12 GND GND J13 GND GND J14 GND V J15 V DDINT DDINT V J16 ...

Page 45

... PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 34. 400-Ball Metric PBGA Pin Configurations (Bottom View, Summary) REV. 0 Pin No. Pin Name Pin No. V18 L5DAT[1] W18 V19 L5DAT[3] W19 V20 L5DAT[5] W20 GND AV DD AGND I/O SIGNALS –45– ADSP-21160N Pin Name Pin No. DMAR1 Y18 EBOOT Y19 L5CLK Y20 ...

Page 46

... POSITION RELATIVE TO THE PACKAGE EDGES. 4. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.15 OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. Case Temperature 1 Part Number Range ADSP-21160NCB-100 –40°C to 100°C ADSP-21160NKB-100 0°C to 85° Plastic Ball Grid Array (PBGA) package. OUTLINE DIMENSIONS ...

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