ADSP-21369BSWZ-2A Analog Devices Inc, ADSP-21369BSWZ-2A Datasheet
ADSP-21369BSWZ-2A
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ADSP-21369BSWZ-2A Summary of contents
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... On-chip memory—2M bits of on-chip SRAM and 6M bits of on-chip mask programmable ROM Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with unique audiocen- tric peripherals such as the digital applications interface, ...
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... Voltage Controlled Oscillator .................................... 18 Corrected the pins names for the DAI and DPI in 256-Ball BGA_ED Pinout ......................................... 51 208-Lead LQFP_EP Pinout ....................................... 54 Added 366 MHz LQFP EPAD models for the ADSP-21367 and ADSP-21369. For additional specifications for these models, refer to the following: Specifications ......................................................... 16 Clock Input ........................................................... 21 SDRAM Interface Timing (166 MHz SDCLK) ...
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... SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These pro- cessors are source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point proces- ...
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... Digital peripheral interface that includes three timers SHARC FAMILY CORE ARCHITECTURE The ADSP-21367/ADSP-21368/ADSP-21369 are code compati- ble at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21367/ADSP-21368/ ADSP-21369 processors share architectural features with the ...
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... The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har- vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0– ...
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... FFFF 0x000E 1555–0x000F FFFF 1 The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. The SRAM can be configured as a maximum of 64k words of 32-bit data, 128k words of 16-bit data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits ...
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... Arbitration Logic to coordinate core and DMA transfers between internal and external memory over the external port. • A Shared Memory Interface that allows the connection four ADSP-21368 processors to create shared exter- nal bus systems (ADSP-21368 only). SDRAM Controller The SDRAM controller provides an interface four sepa- ...
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... DMA channel that is independent from the processor’s serial ports. For complete information on using the DAI, see the ADSP-21368 SHARC Processor Hardware Reference. Serial Ports The processors feature eight synchronous serial ports (SPORTs) that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ ...
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... full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21367 ADSP-21368/ADSP-21369 SPI-compatible peripheral imple- mentation also features programmable baud rate and clock phase and polarities ...
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... SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the UART. Thirty four channels of DMA are available on the ADSP-2136x processors as shown in Table 6. Table 6. DMA Channels ...
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... VDD Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21367/ ADSP-21368/ADSP-21369 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’ ...
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... ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21367/ADSP-21368/ADSP-21369 architecture and func- tionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-21368 SHARC Processor Hardware Reference and the SHARC Processor Programming Reference. Rev Page July 2009 ® ...
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... The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces- sors use extensive pin multiplexing to achieve a lower pin count. For complete information on the multiplexing scheme, see the ADSP-21368 SHARC Processor Hardware Reference, “System Design” chapter. Description External Address. The processors output addresses for external memory and peripher- als on these pins ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Table 8. Pin Descriptions (Continued) State During/ After Reset Name Type (ID = 00x) 1 SDRAS O/T (pu) Pulled high/ driven high 1 SDCAS O/T (pu) Pulled high/ driven high 1 SDWE O/T (pu) Pulled high/ driven high 1 SDCKE O/T (pu) Pulled high/ driven high 1 SDA10 O/T (pu) Pulled high/ driven low ...
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... I (pd) 2–0 1 RPBA I (pu) 1 The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID 2 Pull-up can be enabled/disabled, value of pull-up cannot be programmed. ADSP-21367/ADSP-21368/ADSP-21369 Description Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board con- nectors only ...
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... ADSP-21367/ADSP-21368/ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ CLKIN 3 V Low Level Input Voltage @ CLKIN ...
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... Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU. 9 Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10 10 See Estimating Power Dissipation for ADSP-21368 SHARC Processors (EE-299) for further information. 11 Characterized, but not tested. 12 Applies to all signal pins ...
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... ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE INFORMATION The information presented in Figure 4 the package branding for the ADSP-21367/ADSP-21368/ ADSP-21369 processors. For a complete listing of product avail- ability, see Ordering Guide on Page 58. a ADSP-2136x tppZ-cc vvvvvv.x n.n #yyww country_of_origin S Figure 4. Typical Package Brand Table 9. Package Brand Information Brand Key ...
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... Note the definitions of the clock periods that are a function of VCO CLKIN and the appropriate ratio control shown in and Table 11. All of the timing specifications for the ADSP-2136x peripherals are defined in relation to t cific timing section for each peripheral’s timing information. Table 11. Clock Periods ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Power-Up Sequencing The timing requirements for processor start-up are given in Table 12. Note that during power-up, a leakage current of approximately 200μA may be observed on the RESET pin Table 12. Power-Up Sequencing Timing Requirements (Processor Start-up) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V ...
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... See Figure 5 on Page 19 for VCO diagram. 9 Actual input jitter should be combined with ac specifications for accurate timing analysis. 10 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. CLKIN t CKH ADSP-21367/ADSP-21368/ADSP-21369 1 2 400 MHz 366 MHz 350 MHz Min Max Min Max ...
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... Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-2136x R1 XTAL CLKIN 1M * ...
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... The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 15. Interrupts Parameter Timing Requirement t IRQx Pulse Width IPW DAI_P20–1 DPI_P14–1 FLAG2–0 (IRQ2–0) ADSP-21367/ADSP-21368/ADSP-21369 Min WRST Figure 9. Reset Min 2 × PCLK t IPW Figure 10 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 16. Core Timer Parameter Switching Characteristic t TMREXP Pulse Width WCTIM FLAG3 (TMREXP) Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. ...
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... For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 19. DAI/DPI Pin to Pin Routing Parameter Timing Requirement t Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid DPIO DAI_Pn DPI_Pn DAI_Pm DPI_Pm ADSP-21367/ADSP-21368/ADSP-21369 Table 18 is Min 2 × t PCLK t PWI Figure 13. Timer Width Capture Timing Min 1.5 t DPIO Figure 14 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 20 ...
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... FLAG3–0 IN Pulse Width FIPW Switching Characteristic t FLAG3–0 OUT Pulse Width FOPW DPI_P14–1 (FLAG3–0 (AMI_DATA7–0) (AMI_ADDR23–0) DPI_P14-1 (FLAG3–0 (AMI_DATA7–0) (AMI_ADDR23–0) ADSP-21367/ADSP-21368/ADSP-21369 ) IN t FIPW ) OUT t FOPW Figure 16. Flags Rev Page July 2009 Min Max 2 × t ...
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... ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Timing (166 MHz SDCLK) The 166 MHz access speed is for a single processor. When mul- tiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz. 1 Table 22. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before SDCLK ...
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... Address Disable After CLKIN Rise DSDCA t Address Enable After CLKIN Rise ENSDCA 1 For f = 400 MHz (SDCLK ratio = 1:2.5). CCLK CLKIN COMMAND SDCLK ADDR COMMAND SDCLK ADDR ADSP-21367/ADSP-21368/ADSP-21369 1 t DSDC t DSDCC t DSDCA t ENSDC t ENSDCA t ENSDCC Figure 18. SDRAM Interface Enable/Disable Timing Rev Page July 2009 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Memory Read Use these specifications for asynchronous interfacing to memo- ries. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. ...
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... Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode. ADDR MSx t DAWL WR t WDE DATA t DAAK ACK RD ADSP-21367/ADSP-21368/ADSP-21369 access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode. Min – 3.1+ W SDCLK 2 t – ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Asynchronous Memory Interface (AMI) Enable/Disable Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 26. AMI Enable/Disable Parameter Switching Characteristics t Address/Control Enable After Clock Rise ENAMIAC t Data Enable After Clock Rise ENAMID t Address/Control Disable After Clock Rise DISAMIAC ...
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... Shared Memory Bus Request Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 27. Multiprocessor Bus Request Parameter Timing Requirements t BRx, Setup Before CLKIN High SBRI t BRx, Hold After CLKIN High HBRI Switching Characteristics t BRx Delay After CLKIN High ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 28. Serial Ports—External Clock ...
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... Data Delay from Late External Transmit FS or External Receive DDTLFSE FS with MCE = 1, MFD = Data Enable for MCE = 1, MFD = 0 DDTENFS 1 The t and t parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. DDTLFSE DDTENFS ADSP-21367/ADSP-21368/ADSP-21369 Min 2 –1 Min 0.5 Rev Page July 2009 Min Max Unit 7 ns 2.5 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 DRIVE DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) t DDTLFSE DRIVE DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) t DDTLFSE NOTES 1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS. ...
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... EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DAI_P20–1 (SCLK, EXT) t DDTEN DAI_P20–1 (FS) DRIVE EDGE DAI_P20–1 (DATA CHANNEL A/B) t DDTIN ADSP-21367/ADSP-21368/ADSP-21369 DRIVE EDGE DAI_P20–1 (SCLK HFSI HOFSE DAI_P20–1 (FS) t HDRI DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT— ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Input Data Port The timing requirements for the IDP are given in signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Table 32. IDP ...
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... DAI_P20–1 (PDAP_CLK) DAI_P20–1 (PDAP_CLKEN) DATA DAI_P20–1 (PDAP_STROBE) ADSP-21367/ADSP-21368/ADSP-21369 chapter of the ADSP-21368 SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the external port DATA31–12 pins or the DAI pins. SAMPLE EDGE t PDCLK t PDCLKW ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Pulse-Width Modulation Generators Table 34. PWM Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Sample Rate Converter—Serial Input Port The SRC input signals SCLK, frame sync (FS), and SDATA are routed from the DAI_P20–1 pins using the SRU. Therefore, the ...
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... DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (SDATA) ADSP-21367/ADSP-21368/ADSP-21369 and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. SAMPLE EDGE t SRCCLK ...
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... ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16, 18, 20 bits. The following sections provide timing for the transmitter. DAI_P20–1 LRCLK DAI_P20–1 SCLK DAI_P20–1 LSB MSB SDATA ...
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... The S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock. Table 38. Oversampling Clock (TxCLK) Switching Characteristics Parameter TxCLK Frequency for TxCLK = 384 × FS TxCLK Frequency for TxCLK = 256 × FS Frame Rate (FS) ADSP-21367/ADSP-21368/ADSP-21369 SAMPLE EDGE t t SITXCLKW SITXCLK t ...
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... ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 39. S/PDIF Receiver Internal Digital PLL Mode Timing ...
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... SDSCIM SPICLK ( (OUTPUT) t SPICLK ( (OUTPUT) MOSI (OUTPUT) CPHASE = 1 MISO (INPUT) MOSI (OUTPUT SSPIDM HSPIDM CPHASE = 0 MISO MSB VALID (INPUT) ADSP-21367/ADSP-21368/ADSP-21369 applies t SPICHM SPICLM t SPICLM SPICHM t HDSPIDM t DDSPIDM MSB t SSPIDM t HSPIDM MSB VALID t DDSPIDM MSB LSB VALID Figure 35. SPI Master Timing Rev Page July 2009 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Slave Table 41. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 SDSCO t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 ...
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... System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0. 2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, EMU. TCK TMS TDI t DTDO TDO SYSTEM INPUTS SYSTEM OUTPUTS ADSP-21367/ADSP-21368/ADSP-21369 t TCK t t STAP HTAP t t SSYS HSYS t DSYS Figure 37 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 OUTPUT DRIVE CURRENTS Figure 38 shows typical I-V characteristics for the output driv- ers and Figure 39 shows typical I-V characteristics for the SDCLK output drivers. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125°C ...
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... Figure 42. Typical Output Rise/Fall Time (20 Min) DDEXT 12 10 RISE y = 0.0467x + 1.6323 FALL 0.045x + 1.524 100 150 LOAD CAPACITANCE (pF) Figure 43. Typical Output Rise/Fall Time (20 Max) DDEXT ADSP-21367/ADSP-21368/ADSP-21369 200 250 200 250 0 Rev Page July 2009 RISE y = 0.0372x + 0.228 FALL y = 0.0277x + 0.369 ...
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... LOAD CAPACITANCE (pF) Figure 47. SDCLK Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature) THERMAL CHARACTERISTICS The ADSP-21367/ADSP-21368/ADSP-21369 processors are rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 43 and Table 44 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... BGA_ED PINOUT The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A01 NC B01 A02 TDI B02 A03 TMS B03 A04 CLK_CFG0 B04 ...
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... V17 DDINT U18 V V18 DDINT U19 DATA0 V19 U20 DATA2 V20 1 The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the LQFP_EP package. 2 Applies to ADSP-21368 models only. Signal Ball No. Signal SDA10 R01 SDWE WR R02 SDRAS V R03 GND DDINT V R04 ...
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... BGA_ED ball configu- ration. Figure 49 shows the top view of the BGA_ED ball configuration BOTTOM VIEW KEY VDD DDINT DDEXT I/O SIGNALS GND NO CONNECT Figure 48. 256-Ball BGA_ED Ball Configuration (Bottom View) ADSP-21367/ADSP-21368/ADSP-21369 VSS Rev Page July 2009 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 208-LEAD LQFP_EP PINOUT The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Lead Signal Lead No. Signal No DDINT DDINT 2 DATA28 44 DATA4 3 DATA27 45 DATA5 4 GND 46 DATA2 DATA3 ...
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... Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued) Lead Signal Lead No. Signal No. 40 DATA6 82 GND CLKIN DDEXT 42 GND 84 XTAL ADSP-21367/ADSP-21368/ADSP-21369 Lead Signal Lead Signal No. No. 124 FLAG0 166 GND 125 DAI_P20 (SFS5) 167 V DDINT 126 GND 168 TMS Rev Page July 2009 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE DIMENSIONS The ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball RoHS compliant and leaded BGA_ED, and 208-lead RoHS compliant LQFP_EP packages. 1.60 MAX 0.75 0.60 0.45 1.00 REF SEATING PLANE 1.45 0.20 1.40 0.15 1.35 0.09 0.15 7° 0.10 3.5° 0.05 0.08 0° ...
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... IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 47. BGA_ED Data for Use with Surface-Mount Design Package Ball Attach Type 256-Lead Ball Grid Array BGA_ED Solder Mask Defined (SMD) (BP-256) ADSP-21367/ADSP-21368/ADSP-21369 24.13 BSC SQ 1.27 BSC ...
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... ADSP-21369KSWZ-5A 0°C to +70°C 3 ADSP-21369BSWZ-1A –40°C to +85°C 3 ADSP-21369BSWZ-2A –40°C to +85°C 1 Referenced temperature is ambient temperature. 2 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC. ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Rev Page July 2009 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05267-0-7/09(E) Rev Page July 2009 ...