ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet
ADSP-BF504BCPZ-4
Specifications of ADSP-BF504BCPZ-4
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ADSP-BF504BCPZ-4 Summary of contents
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... ADSP-BF506F processors) Internal ADC (available on ADSP-BF506F processor) Off-chip voltage regulator interface 88-lead (12 mm × 12 mm) LFCSP package for ADSP-BF504 and ADSP-BF504F processors 120-lead (14 mm × 14 mm) LQFP package for ADSP-BF506F processor MEMORY 68K bytes of L1 SRAM (processor core-accessible) memory (See Table 1 on Page 3 ...
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... UART Ports (UARTs) .......................................... 11 Parallel Peripheral Interface (PPI) ........................... 11 RSI Interface ...................................................... 12 Controller Area Network (CAN) Interface ................ 12 TWI Controller Interface ...................................... 13 Ports ................................................................ 13 Dynamic Power Management ................................ 13 ADSP-BF50x Voltage Regulation ............................ 15 Clock Signals ..................................................... 15 Booting Modes ................................................... 16 Instruction Set Description ................................... 17 Development Tools ............................................. 17 Designing an Emulator-Compatible Processor Board (Target) ................................... 17 ADC and ACM Interface ...................................... 18 Internal ADC ...
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... Table 16, and Table 24 The ADSP-BF50x processors include an interface to an off-chip voltage regulator in support of the processor’s dynamic power management capability. Rev Page December 2010 ® support; a par- on Page 1) ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F BLACKFIN PROCESSOR CORE As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers ...
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... Internal (Core-Accessible) Memory The processor has three blocks of core-accessible memory, providing high-bandwidth access to the core. ADSP-BF504/ADSP-BF504F/ADSP-BF506F The first block is the L1 instruction memory, consisting of 32K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Booting The processor contains a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. If the processor is configured to boot from boot ROM memory space, the proces- sor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page ...
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... DMA Channel 10 (UART1 Rx) DMA Channel 11 (UART1 Tx) CAN Receive CAN Transmit TWI Port F Interrupt A Port F Interrupt B Reserved Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Port G Interrupt A Port G Interrupt B MDMA Stream 0 ADSP-BF504/ADSP-BF504F/ADSP-BF506F General-Purpose Peripheral Interrupt (at Reset) Interrupt ID IVG7 0 IVG7 1 IVG7 2 IVG7 3 IVG7 4 IVG7 5 IVG7 6 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 3. System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Source MDMA Stream 1 Software Watchdog Timer Port H Interrupt A Port H Interrupt B ACM Status Interrupt ACM Interrupt Reserved Reserved PWM0 Trip Interrupt PWM0 Sync Interrupt PWM1 Trip Interrupt PWM1 Sync Interrupt RSI Mask 1 Interrupt ...
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... FLASH MEMORY The ADSP-BF504F and ADSP-BF506F processors include an on-chip 32M bit (×16, multiple bank, burst) Flash memory. The features of this memory include: • Synchronous/asynchronous read • Synchronous burst read mode: 50 MHz • Asynchronous/synchronous read mode • Random access times • Synchronous burst read suspend • ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F The timers can generate interrupts to the processor core provid- ing periodic events for synchronization, either to the system clock count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts ...
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... H.100, H.110, MVIP-90, and HMVIP standards. SERIAL PERIPHERAL INTERFACE (SPI) PORTS The ADSP-BF50x processors have two SPI-compatible ports that enable the processor to communicate with multiple SPI- compatible devices. The SPI interface uses three pins for transferring data: two data pins MOSI (Master Output-Slave Input) and MISO (Master Input-Slave Output) and a clock pin, serial clock (SCK) ...
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... CE-ATA command completion signal recognition and disable CONTROLLER AREA NETWORK (CAN) INTERFACE The ADSP-BF50x processors provide a CAN controller that is a communication controller implementing the Controller Area Network (CAN) V2.0B protocol. This protocol is an asynchro- nous communications protocol used in both industrial and automotive control systems ...
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... This allows a sin- gle controller to support different drivers and CAN networks. The ADSP-BF50x CAN module represents the controller part of the interface. This module’s network I single transmit output and a single receive input, which connect to a line transceiver ...
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... Hibernate Disabled — Disabled Disabled Off For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-BF50x Blackfin Pro- cessor Hardware Reference. Sleep Operating Mode—High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK) ...
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... Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices web- site (www.analog.com)—use site search on “EE-168.” The Blackfin core runs at a different clock rate than the on-chip peripherals ...
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... The SSEL value can be 1 This boot mode applies to ADSP-BF504F and ADSP-BF506F processors only. The boot modes listed in nisms for automatically loading the processor’s internal and external memories after a reset. By default, all boot modes use the slowest meaningful configuration settings. Default settings can be altered via the initialization code feature at boot time ...
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... Blackfin processors also fully emulates the ADSP-BF50x processors. EZ-KIT Lite Evaluation Board For evaluation of ADSP-BF50x processors, use the EZ-KIT Lite boards soon to be available from Analog Devices. When these evaluation kits are available, order using part number ADZS-BF506-EZLITE. The boards come with on-chip emulation capabilities and is equipped to enable software development ...
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... The serial interface on the ADC allows the part to be directly connected to the ADSP-BF504, ADSP-BF504F, and ADSP-BF506F processors using serial interface protocols. Figure 6 shows how to connect an external ADC to the ACM and one of the two SPORTs on the ADSP-BF504 or ADSP-BF504F processors. ADSP-BF504 / ADSP-BF504F (EXTERNAL) Figure 6. ADC (External), ACM, and SPORT Connections The ADC is integrated into the ADSP-BF506F product ...
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... SCLK burst. A Blackfin driver for the ADC is available to download at www.analog.com. INTERNAL ADC An ADC is integrated into the ADSP-BF506F product. All ADC signals are connected out to package pins to enable maximum interconnect flexibility in mixed signal applications. The internal ADC is a dual, 12-bit, high speed, low power, suc- cessive approximation ADC that operates from a single 2 ...
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... These low ESR and ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. RELATED DOCUMENTS The following publications that describe the ADSP-BF50x pro- cessors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: • ...
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... SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF50x processors are listed in Table 11. All pins for the ADC (ADSP-BF506F processor only) are listed in Table 12. In order to maintain maximum function and reduce package size and pin count, some pins have multiple, multiplexed func- tions. In cases where pin function is reconfigurable, the default state is shown in plain text, while the alternate functions are shown in italics ...
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... TDO TDI TMS TRST EMU Clock CLKIN XTAL EXTCLK Mode Controls RESET NMI BMODE2–0 ADSP-BF50x Voltage Regulation I/F EXT_WAKE PG Power Supplies V DDEXT V DDINT V DDFLASH GND Type Function I/O GPIO/UART0 RTS/SD Data 6/Timer0/PPI FS1/Count Up Dir 1 I/O GPIO/UART0 CTS/SD Data 7/Timer1/PPI FS2/Count Down Dir 1 ...
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... Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only) Signal Name Type Function DGND G Digital Ground. This is the ground reference point for all digital circuitry on the internal ADC. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only) (Continued) Signal Name Type Function Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked OUT OUT out on the falling edge of the ADSCLK input and 14 ADSCLKs are required to access the data. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs ...
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... For ADSP-BF504, V pins should be connected to GND. DDFLASH 4 Bidirectional pins (PF15–0, PG15–0, PH2–0) and input pins (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF50x processors are 3.3 V tolerant (always accept up to 3.6 V maximum V ). Voltage compliance (on outputs Parameter value applies to all input and bidirectional pins, except SDA and SCL ...
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... ADSP-BF50x processors. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 16). Table 15 locked loop operating conditions. Table 14. Core Clock (CCLK) Requirements—ADSP-BF50x Processors—All Speed Grades Parameter f Core Clock Frequency (V CCLK DDINT Core Clock Frequency (V ...
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... Current in Deep Sleep Mode f DDDEEPSLEEP DDINT Current DDINT DDINT I Flash Memory Supply Current 1 DDFLASH1 — Asynchronous Read (5 MHz 11 NORCLK ) Flash Memory Supply Current 1 — Synchronous Read (50 MHz 11 NORCLK ) ADSP-BF504/ADSP-BF504F/ADSP-BF506F Test Conditions –0.5 mA DDEXT 2. –0.5 mA 2.0 DDEXT 3 –0.5 mA DDEXT 1.7 V/2.25 V/3.0 V, DDEXT ...
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... Applies to bidirectional pins SCL and SDA. 5 Applies to all signal pins, except SCL and SDA. 6 Guaranteed, but not tested. 7 See the ADSP-BF50x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 8 Applies to V supply only. Clock inputs are tied high or low. DDEXT 9 Guaranteed maximum specifications ...
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... Valid temperature and voltage ranges are model-specific. See Table 19. ADSP-BF50x Dynamic Current in CCLK Domain (mA, with ASF = 1.0) f CCLK 2 (MHz) 1.10 V 1.15 V 400 N/A N/A 350 N/A N/A 300 N/A N/A 250 43 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F PROCESSOR—ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 20 nent damage to the device. These are stress ratings only. Functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. ADSP-BF504/ADSP-BF504F/ADSP-BF506F PACKAGE INFORMATION The information presented in details about the package branding for the ADSP-BF50x processors. Figure 9. Product Information on Package Table 23. Package Brand Information Brand Key ADSP-BF50x ...
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... If the DF bit in the PLL_CTL register is set, the minimum f 5 Applies after power-up sequence is complete. See 6 The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or CLKOUT. This parameter applies when EXTCLK is programmed to output CLKBUF. t CKIN ...
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... CLKOUT Width Low SCLKL 1 The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKOUT pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or CLKOUT. This parameter applies when EXTCLK is programmed to output CLKOUT. 2 The t value is the inverse of the f specification. Reduced supply voltages affect the best-case value listed here. ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Parallel Peripheral Interface Timing Table 27 and Figure 14 on Page 34, Figure 20 on Page Figure 22 on Page 40 describe parallel peripheral interface operations. Table 27. Parallel Peripheral Interface Timing Parameter Timing Requirements 1 t PPI_CLK Width PCLKW 1 t PPI_CLK Period PCLK Timing Requirements—GP Input and Frame Capture Modes ...
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... SDRPE PPI_DATA Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 PPI_DATA Figure 17. PPI GP Tx Mode with Internal Frame Sync Timing Rev Page December 2010 ADSP-BF504/ADSP-BF504F/ADSP-BF506F t t HFSPE PCLKW t PCLK t PCLK t HDRPE DATA DRIVEN t ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F RSI Controller Timing Table 28 and Figure 18 describe RSI Controller Timing. Table 29 and Figure 19 describe RSI controller (high speed) timing. Table 28. RSI Controller Timing Parameter Timing Requirements t Input Setup Time ISU t Input Hold Time IH Switching Characteristics 1 f Clock Frequency Data Transfer Mode ...
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... Output Delay Time During Data Transfer Mode ODLY t Output Hold Time 1 SD_CLK t THL t WL INPUT OUTPUT NOTES: 1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. 2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. ADSP-BF504/ADSP-BF504F/ADSP-BF506F TLH ISU ODLY Figure 19. RSI Controller Timing (High-Speed Mode) Rev Page December 2010 Min Max 5. ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Serial Ports Table 30 through Table 33 on Page 40 and through Figure 22 on Page 40 describe serial port operations. Table 30. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx HFSE t Receive Data Setup Before RSCLKx SDRE ...
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... Data Disable Delay from External TSCLKx DDTTE t Data Enable Delay from Internal TSCLKx DTENI t Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge. TSCLKx DTx ADSP-BF504/ADSP-BF504F/ADSP-BF506F DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE RSCLKx RFSx (OUTPUT) t HFSI RFSx (INPUT) t HDRI DRx DATA TRANSMIT— ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 33. Serial Ports — External Late Frame Sync Parameter Switching Characteristics t Data Delay from Late External TFSx DDTLFSE or External RFSx in Multi-channel Mode With MFD = 0 t Data Enable from External RFSx in Multi-channel Mode With DTENLFSE 1, 2 MFD = 0 1 When in multi-channel mode, TFSx enable and TFSx valid follow external RFSx/TFSx setup to RSCLKx/TSCLKx > ...
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... SCK Edge to Data Out Invalid (Data Out Hold) HDSPIDM (OUTPUT) t SDSCIM SPIxSCK (OUTPUT) SPIxMOSI (OUTPUT) CPHA = 1 SPIxMISO (INPUT) SPIxMOSI (OUTPUT) t SSPIDM CPHA = 0 SPIxMISO (INPUT) ADSP-BF504/ADSP-BF504F/ADSP-BF506F Min 11.6 –1.5 2 × t SCLK 2 × t SCLK 2 × t SCLK 4 × t SCLK 2 × t SCLK 2 × t SCLK 0 –1.0 t ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Serial Peripheral Interface (SPI) Port—Slave Timing Table 35 and Figure 24 describe SPI port slave operations. Table 35. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period SPICLK ...
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... Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF50x Hardware Reference Manual. General-Purpose Port Timing Table 36 and Figure 25 describe general-purpose port operations. Table 36. General-Purpose Port Timing Parameter Timing Requirement t General-Purpose Port Pin Input Pulse Width ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Timer Cycle Timing Table 37 and Figure 26 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency of (f /2) MHz. SCLK Table 37. Timer Cycle Timing Parameter Timing Requirements ...
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... Counter Input Setup Time Before CLKOUT High CIS t Counter Input Hold Time After CLKOUT High CIH 1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs. CLKOUT CUD/CDG/CZM ADSP-BF504/ADSP-BF504F/ADSP-BF506F V DDEXT Min Figure 27. Timer Clock Timing V DDEXT Min t ...
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... PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL. 2 When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is asynchronous to the peripheral clock. For more information, see the ADSP-BF50x Blackfin Processor Hardware Reference. CLKOUT PWMx_SYNC ...
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... CS Active Edge Delay After Falling Edge of CLKOUT DCS t The Delay Between the Active Edge of CS and the First Edge of DCSACLK ACLK CLKOUT t DCS t DCSACLK ACLK ACM CONTROLS DRxPRI/ DRxSEC ADSP-BF504/ADSP-BF504F/ADSP-BF506F + 2 V DDEXT Min 8 – 5 ACLK SDR Figure 30. ACM Timing Rev Page December 2010 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F JTAG Test And Emulation Port Timing Table 42 and Figure 31 describe JTAG port operations. Table 42. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... PROCESSOR—OUTPUT DRIVE CURRENTS Figure 32 through Figure 40 show typical current-voltage char- acteristics for the output drivers of the ADSP-BF50xF processors. 240 200 160 120 –40 –80 –120 –160 –200 –240 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 32. Driver Type B Current (3 160 120 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F 0 –10 –20 –30 –40 –50 –60 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 38. Driver Type D Current (3 –5 –10 –15 –20 –25 –30 –35 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 39. Driver Type D Current (2 –2 –4 –6 –8 –10 –12 –14 – ...
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... LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 43. Equivalent Device Loading for AC Measurements (Includes All Fixtures) ADSP-BF504/ADSP-BF504F/ADSP-BF506F is the DIS DECAY . This decay time L ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F 100 LOAD CAPACITANCE (pF) Figure 47. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (1 100 LOAD CAPACITANCE (pF) Figure 48. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2 100 LOAD CAPACITANCE (pF) Figure 49. Driver Type C Typical Rise and Fall Times (10%–90%) vs. ...
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... Table 46 shows the ADC absolute maximum ratings. Table 46. Flash Absolute Maximum Ratings Parameter Junction Temperature While Biased Storage Temperature Range Flash Memory Supply Voltage (V ) –0 +2.45 V DDFLASH ADSP-BF504/ADSP-BF504F/ADSP-BF506F 1 Rating See Table 20 on Page 30 See Table 20 on Page 30 Rev Page December 2010 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC—SPECIFICATIONS Specifications are subject to change without notice. ADC—OPERATING CONDITIONS Parameter Conditions MHz DRIVE ADSCLK internal or external reference = 2.5 V ± 1% unless otherwise noted MHz, f ADSCLK internal or external reference = 2.5 V ± 1% unless otherwise noted MHz, f ADSCLK internal or external reference = 2.5 V ± 1% ...
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... Spurious-Free Dynamic Range (SFDR) 1,2 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Channel-to-Channel Isolation SAMPLE AND HOLD 2 Aperture Delay 2 Aperture Jitter 2 Aperture Delay Matching Full Power Bandwidth ADSP-BF504/ADSP-BF504F/ADSP-BF506F Specification Unit V – 0.2 V min DRIVE 0.4 V max ±1 μA max 7 pF typ Straight (natural) binary ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 48. Operating Conditions (ADC Performance/Accuracy) (Continued) Parameter DC ACCURACY Resolution 1 Integral Nonlinearity (INL Differential Nonlinearity (DNL) Straight Natural Binary Output Coding 1,2 Offset Error 1,2 Offset Error Match 1,2 Gain Error 1,2 Gain Error Match Twos Complement Output Coding 1,2 Positive Gain Error ...
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... Digital Output Voltage to GND V to AGND REF Input Current to Any ADC Pin 1 Except Supplies Storage Temperature Range Junction Temperature Under Bias 1 Transient currents 100 mA will not cause latch up. ADSP-BF504/ADSP-BF504F/ADSP-BF506F Unit Test Conditions / Comments MHz min/max ns max t = 1/f ADSCLK ADSCLK ns max MHz, f ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC—TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A –60 INTERNAL REFERENCE –70 –80 EXTERNAL REFERENCE –90 –100 –110 100mV p-p SINE WAVE DECOUPLING SINGLE-ENDED MODE –120 0 200 400 600 800 1000 1200 1400 1600 1800 SUPPLY RIPPLE FREQUENCY (kHz) Figure 50. PSRR vs. Supply Ripple Frequency Without Supply Decoupling – ...
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... CURRENT LOAD (PA) Figure 58. V vs. Reference Output Current Drive REF ADSP-BF504/ADSP-BF504F/ADSP-BF506F 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 2046 2.0 2.5 Figure 59. Histogram of Codes for 10k Samples in Differential Mode 10000 9000 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F ADC—TERMINOLOGY Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the mea- sured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC trans- fer function ...
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... V ( ppm ) HYS REF ADSP-BF504/ADSP-BF504F/ADSP-BF506F where: ). The result REF ADC—THEORY OF OPERATION The following sections describe the ADC theory of operation. Circuit Information The ADC is a fast, micropower, dual, 12-bit, single-supply, ADC that operates from a 2 5.25 V supply. When oper- ated from supply, the ADC is capable of throughput rates MSPS when provided with a 32 MHz clock, and a throughput rate ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F When the ADC starts a conversion (see version Phase)), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The con- trol logic and the charge redistribution DACs are used to add ...
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... REF If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias up this sig- nal to make it correctly formatted for the ADC. a typical connection diagram when operating the ADC in sin- gle-ended mode. ADSP-BF504/ADSP-BF504F/ADSP-BF506F = 300Ÿ SOURCE +1.25V 0V – ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F supply using the range or 2 × V REF The common mode must be in this range to guarantee the func- tionality of the ADC. When a conversion takes place, the common mode is rejected, resulting in a virtually noise free signal of amplitude –V +V corresponding to the digital codes 4096. If the 2 × ...
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... V (V) REF Figure 74. V Input Voltage Range vs. V IN- Pseudo Differential Mode with V ADSP-BF504/ADSP-BF504F/ADSP-BF506F 3.75V 2.5V 1.25V 1 V ADC IN+ 3.75V 2.5V V 1.25V REF V (D A/D B) CAP CAP IN– 0.47μF ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F required acquisition time for the next sampling instant at Point B; therefore, the analog inputs are configured as differential for that conversion ACQ ADSCLK SGL/DIFF Figure 77. Selecting Differential or Single-Ended Configuration The channels used for simultaneous conversions are selected via the multiplexer address input pins A2. The logic states of these pins also need to be established prior to the acquisition time ...
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... Similarly, if already in a power-down mode, CS can control whether the device returns to normal operation or remains in power-down. These modes of operation are designed to provide flexible power man- ADSP-BF504/ADSP-BF504F/ADSP-BF506F agement options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing applica- tion requirements. ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F down for a relatively long duration between these bursts of sev- eral conversions. When the ADC is in partial power-down, all analog circuitry is powered down except for the on-chip refer- ence and reference buffer. To enter partial power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the sec- ...
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... ADSCLK falling edge (see (Entering Partial Power-Down Mode)). Alternatively intended to place the part in full power-down mode when the supplies are applied, then three dummy cycles must be initiated. ADSP-BF504/ADSP-BF504F/ADSP-BF506F THE PART ENTERS THE PART BEGINS TO POWER UP. 10 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F maximum ADSCLK frequency and an ADSCLK frequency that scales with the sampling rate with V DD respectively. In all cases, the internal reference was used. 10 25°C A 9.5 9.0 8.5 VARIABLE ADSCLK 8.0 7.5 7.0 24MHz ADSCLK 6.5 6.0 5.5 5.0 0 200 400 ...
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... DB11 0 DB10 D B OUT THREE- STATE 2 LEADING ZEROS ADSCLK ZERO DB11 DB10 DB9 OUT THREE- STATE 2 LEADING ZEROS Figure 88. Reading Data from Both ADCs on One D ADSP-BF504/ADSP-BF504F/ADSP-BF506F DB9 DB8 DB2 DB1 Figure 87. Serial Interface Timing Diagram ZERO ZERO ZERO ZERO A 2 TRAILING ZEROS ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F 120-LEAD LQFP LEAD ASSIGNMENT Table 54 lists the LQFP leads by signal mnemonic. Page 73 lists the LQFP leads by lead number. Table 54. 120-Lead LQFP Lead Assignment (Alphabetical by Signal) Signal Lead No. Signal A0 100 NMI A2 97 PF0 AGND 73 PF1 AGND 78 PF2 AGND 79 PF3 AGND 82 PF4 ...
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... DDEXT DDINT DDFLASH DDEXT 27 PG0 57 28 PG1 58 29 PG2 DDEXT * Pin no. 121 is the GND supply (see Figure 89 ** Pin no. 122 is the AGND supply (see Figure 89 ADSP-BF504/ADSP-BF504F/ADSP-BF506F Signal Lead No. PG3 61 PG4 62 TDI 63 TCK 64 TMS 65 TDO 66 TRST 67 PG5 68 PG6 69 PG7 DDEXT V 72 DDINT PG8 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Figure 89 shows the top view of the 120-lead LQFP package lead configuration. PIN 120 PIN 1 PIN 1 INDICATOR 120-LEAD LQFP TOP VIEW PIN 30 PIN 31 Figure 89. 120-Lead LQFP Package Lead Configuration (Top View) Figure 90 shows the bottom view of the 120-lead LQFP package lead configuration. ...
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... NC 48 PG0 NC 64 PG1 NC 65 PG2 NC 66 PG3 NMI 1 PG4 PF0 76 PG5 PF1 77 PG6 PF2 80 PG7 PF3 81 PG8 * Pin no the GND supply (see Figure ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 57 on Lead No. Signal 82 PG9 83 PG10 85 PG11 86 PG12 87 PG13 88 PG14 4 PG15 6 PH0 8 PH1 9 PH2 11 RESET 12 SCL 63 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F Table 57. 88-Lead LFCSP Lead Assignment (Numerical by Lead Number) Lead No. Signal Lead No. 1 NMI 23 2 RESET 24 3 GND 25 4 PF10 DDEXT 6 PF11 28 7 GND 29 8 PF12 30 9 PF13 DDEXT 11 PF14 33 12 PF15 DDEXT DDINT DDFLASH DDEXT 17 PG0 39 18 PG1 40 19 PG2 ...
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... LFCSP pin configuration. PIN 88 PIN 1 PIN 1 INDICATOR 88-LEAD LFCSP TOP VIEW PIN 22 PIN 23 Figure 91. 88-Lead LFCSP Lead Configuration (Top View) ADSP-BF504/ADSP-BF504F/ADSP-BF506F Figure 92 shows the bottom view of the LFCSP lead configuration. PIN 67 PIN 66 PIN 66 PIN 45 PIN 45 PIN 44 Figure 92 ...
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... ADSP-BF504/ADSP-BF504F/ADSP-BF506F OUTLINE DIMENSIONS Dimensions in Figure 93 (for the 120-lead LQFP) and in Figure 94 (for the 88-lead LFCSP) are shown in millimeters. 1.60 MAX 1.00 REF 0.75 0.60 0.45 1.45 1.40 1.35 0.15 0.10 0.05 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET ...
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... PIN 1 INDICATOR TOP VIEW 0.70 0.65 12° MAX 0.85 0.60 0.80 0.75 SEATING 0.30 PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VRRD. Rev Page December 2010 ADSP-BF504/ADSP-BF504F/ADSP-BF506F 0.60 MAX 0.60 MAX 67 66 0.50 11.85 BSC 11.75 SQ EXPOSED PAD 11.65 0.50 0. 0.30 BOTTOM VIEW ...
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... Temperature range 0°C to +70°C is classified as commercial, and temperture range –40°C to +85°C is classified as industrial. ORDERING GUIDE Temperature 1,2 Model Range ADSP-BF504BCPZ-3F –40°C to +85°C ADSP-BF504BCPZ-4 –40°C to +85°C ADSP-BF504BCPZ-4F –40°C to +85°C ADSP-BF504KCPZ-3F 0°C to +70°C ADSP-BF504KCPZ-4 0°C to +70°C ADSP-BF504KCPZ-4F 0°C to +70° RoHS compliant part. ...