ADV3002BSTZ-RL Analog Devices Inc, ADV3002BSTZ-RL Datasheet
ADV3002BSTZ-RL
Specifications of ADV3002BSTZ-RL
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ADV3002BSTZ-RL Summary of contents
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FEATURES 4 inputs, 1 output HDMI/DVI links ±8 kV ESD protection on input pins HDMI 1.3a receive and transmit compliant Supports 250 Mbps to 2.25 Gbps data rates and beyond Supports 25 MHz to 225 MHz pixel clocks and beyond ...
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ADV3002 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 TMDS Performance Specifications ............................................ 3 Auxiliary Channel Performance Specifications........................ 3 ...
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SPECIFICATIONS T = 27°C, AVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, data rate = 2.25 Gbps, differential input swing = 1000 mV, TMDS outputs A terminated with external 50 Ω resistors to 3.3 V, unless ...
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ADV3002 Parameter Test Conditions/Comments Rise Time 10 PULL-UP Fall Time 90 PULL-UP Pull-Up Resistance Leakage Off-leakage test conditions HOT PLUG DETECT Output Low Voltage 800 Ω ...
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ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating AVCC to AVEE 3.7 V P5V_x 5.8 V AMUXVCC AVCC − 0.3 V < AMUXVCC < 5.8 V Internal Power Dissipation 1.2 W TMDS Single-Ended Input AVCC − 1.4 V < V Voltage ...
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ADV3002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN_B_CLK– 1 IN_B_CLK+ 2 HPD_B 3 IN_B_DATA0– 4 IN_B_DATA0+ 5 HPD_A 6 IN_B_DATA1– 7 IN_B_DATA1+ 8 AVCC 9 IN_B_DATA2– 10 IN_B_DATA2+ 11 SEL0 12 IN_A_CLK– 13 IN_A_CLK+ 14 SEL1 15 IN_A_DATA0– 16 IN_A_DATA0+ 17 ...
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Table 6. Pin Function Descriptions Pin No. Mnemonic 1 IN_B_CLK− 2 IN_B_CLK+ 3 HPD_B 4 IN_B_DATA0− 5 IN_B_DATA0+ 6 HPD_A 7 IN_B_DATA1− 8 IN_B_DATA1+ 9, 18, 33, 43, 52 AVCC 10 IN_B_DATA2− 11 IN_B_DATA2+ 12 SEL0 13 IN_A_CLK− 14 IN_A_CLK+ ...
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ADV3002 Pin No. Mnemonic 59 IN_C_DATA2− 60 IN_C_DATA2+ 61 EDID_SCL 62 EDID_SDA 63 EDID_ENABLE 64 AMUXVCC 65 CEC_OUT 66 CEC_IN 67 DDC_SCL_COM 68 DDC_SDA_COM 69 DDC_SCL_D 70 DDC_SDA_D 71 DDC_SCL_C 72 DDC_SDA_C 73 DDC_SCL_B 74 DDC_SDA_B 75 DDC_SCL_A 76 DDC_SDA_A ...
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TYPICAL PERFORMANCE CHARACTERISTICS T = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 A data rate = 2.25 Gbps, TMDS outputs terminated with external 50 ...
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ADV3002 1.0 ALL CABLES = 24 AWG 0.9 0.8 0.7 1080p, 12-BIT 0.6 1080p, 10-BIT 1080p, 8-BIT 0.5 720p 0.4 0.3 0.2 0 INPUT CABLE LENGTH (m) Figure 8. Deterministic Jitter vs. Input Cable Length 100 90 ...
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EQ = 18dB 0.2 0.4 0.6 0.8 1.0 1.2 1.4 DIFFERENTIAL INPUT SWING (V) Figure 14. Deterministic Jitter vs. Input Swing 250 200 150 100 DATA RISE TIME ...
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ADV3002 THEORY OF OPERATION The primary function of the ADV3002 is to switch up to four HDMI/DVI sources to one HDMI/DVI sink. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed signals. The ...
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HDMI/DVI receiver. If both the internal terminations are enabled and external terminations are present, set the output current level programming the TX_OCL bit of the TMDS output control register, as shown in Table 10 (20 mA ...
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ADV3002 Source Physical Address Assignment In HDTV applications where the CEC function is available, the EDID contains the source physical address (SPA); a unique value for each HDMI port. Because the memory in the ADV3002 is volatile, the SPA must ...
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EDID Replication with External EEPROM The ADV3002 has dedicated pins to interface to an external EDID EEPROM: EDID_SDA and EDID_SCL. In the default configuration, after the first hot plug event or system power-up, the internal I master in the ADV3002 ...
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ADV3002 LOSS OF SIGNAL DETECT The TMDS clock line of each HDMI input has a loss of signal (LOS) monitor attached to it. The purpose of the LOS monitor is to determine if there is activity in the HDMI link. ...
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SERIAL CONTROL INTERFACE RESET On initial power-up any point in operation, the ADV3002 register set can be restored to the default values by pulling the RESETB pin low according to the specification in Table 3. During normal operation, ...
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ADV3002 I2C_SCL GENERAL CASE FIXED PART START ADDR ADDR I2C_SDA EXAMPLE I2C_SDA 1 2 READ PROCEDURE To read data from the ADV3002 register set microcontroller) needs to send the appropriate control signals to the ADV3002 slave ...
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REGISTER MAP Table 10. Register Map Register Address Default Name 0x00 0x00 Channel select control 0x01 0x07 TMDS output control 0x02 0x02 TMDS input control 0x03 0x0F TMDS input termination control 0x04 0x07 Auxiliary buffer enables 0x05 0x05 Hot plug ...
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ADV3002 Register Address Default Name 0x07 0x00 Loss of signal detect control 0x0E 0x00 EDID replication mode (write only) 0x0F 0x00 EDID EEPROM write protect password (write only) 0x10 0x00 Loss of signal detect status 0xFE 0x03 Revision 0xFF 0xC2 ...
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APPLICATIONS INFORMATION HDMI MULTIPLEXER FOR ADVANCED TV The ADV3002 is a complete HDMI/DVI link switch featuring equalized TMDS inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated ...
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ADV3002 OPTION 1 TMDS D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V 1kΩ 47kΩ HPD DDC_SCL DDC_SDA CEC TMDS D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– 5V 1kΩ 47kΩ HPD DDC_SCL DDC_SDA CEC TMDS D2+ D2– D1+ D1– ...
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OPTION 2 AMUXVCC 1µF 0.01µF AMUXVCC TMDS D2+ IN_A_DATA2+ D2– IN_A_DATA2– D1+ IN_A_DATA1+ D1– IN_A_DATA1– D0+ IN_A_DATA0+ D0– IN_A_DATA0– CLK+ IN_A_CLK+ CLK– IN_A_CLK– 5V P5V_A 1kΩ 47kΩ 47kΩ HPD HPD_A DDC_SCL DDC_SCL_A DDC_SDA DDC_SDA_A CEC TMDS D2+ IN_B_DATA2+ D2– IN_B_DATA2– ...
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ADV3002 CABLE LENGTHS AND EQUALIZATION The ADV3002 offers two levels of programmable equalization for the high speed inputs and 18 dB. The equalizer of the ADV3002 supports video data rates 2.25 Gbps and can equalize ...
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A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on ...
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ADV3002 bus should suffice. The HDMI 1.3a specification, however, places a strict 50 pF limit on the amount of capacitance that can be measured on either SDA or SCL at the HDMI input connector. This 50 pF limit includes the ...
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... SEATING 0.10 0.05 PLANE COPLANARITY VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range ADV3002BSTZ 1 0°C to +85°C ADV3002BSTZ-RL 1 0°C to +85°C ADV3002-EVALZ RoHS Compliant Part. 1 0.75 1.60 0.60 MAX 0. PIN 1 (PINS DOWN) 0.20 0.09 7° ...
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... ADV3002 NOTES Purchase of licensed I C components of Analog Devices Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...