ADV7127KRU50 Analog Devices Inc, ADV7127KRU50 Datasheet - Page 7

Digital/Analog Converter IC Package/Case:24-TSSOP

ADV7127KRU50

Manufacturer Part Number
ADV7127KRU50
Description
Digital/Analog Converter IC Package/Case:24-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV7127KRU50

Leaded Process Compatible
No
A/d, D/a Features
CMOS, 240 MHz 10-Bit High Speed Video DAC
Peak Reflow Compatible (260 C)
No
Resolution
10-Bit
Settling Time
15nS
Rohs Status
RoHS non-compliant
Number Of Bits
10
Data Interface
Parallel
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
30mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADV7127KRU50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADV7127KRU50-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
3.3 V TIMING SPECIFICATIONS
Parameter
ANALOG OUTPUTS
CLOCK CONTROL
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
REV. 0
Timing specifications are measured with input levels of 3.0 V (V
These maximum and minimum specifications are guaranteed over this range.
Temperature range: T
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
Measured from 50% point of full-scale transition to 2% of final value.
Guaranteed by characterization.
f
This power-down feature is only available on the ADV7127 in the TSSOP package.
CLK
Analog Output Delay, t
Analog Output Rise/Fall Time, t
Analog Output Transition Time, t
Analog Output Skew, t
f
f
f
Data and Control Setup, t
Data and Control Hold, t
Clock Pulsewidth High, t
Clock Pulsewidth Low t
Clock Pulsewidth High t
Clock Pulsewidth Low t
Clock Pulsewidth High t
Clock Pulsewidth Low t
Pipeline Delay, t
PSAVE Up Time, t
PDOWN Up Time, t
CLK
CLK
CLK
max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization.
7
7
7
MIN
PD
6
to T
10
6
11
MAX
9
8
6
6
5
5
5
4
4
ANALOG OUTPUTS
6
6
6
4
2
6
6
: –40 C to +85 C at 50 MHz and 140 MHz, 0 C to +70 C at 240 MHz.
2
6
6
DIGITAL INPUTS
(I
OUT
7
4
(D9–D0)
CLOCK
,
8
5
I
OUT
)
NOTES:
1. OUTPUT DELAY (
2. OUTPUT RISE/FALL TIME (
3. TRANSITION TIME (
EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANSITION.
90% POINTS OF FULL SCALE TRANSITION.
SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
1
(V
otherwise noted, T
Min
1.5
2.5
2.85
2.85
8.0
8.0
1.0
t
4
AA
IH
Figure 1. Timing Diagram
= +3.0 V–3.6 V
t
) and 0 V (V
3
t
5
t
6
) MEASURED FROM THE 50% POINT OF THE RISING
t
8
) MEASURED FROM THE 50% POINT OF FULL
Typ
7.5
1.0
15
1
1.1
1.4
1.0
4
320
IL
t
–7–
) 0 for both 5 V and 3.3 V supplies.
7
J MAX
) MEASURED BETWEEN THE 10% AND
DATA
2
t
, V
1
REF
= 110 C)
= 1.235 V, R
t
Max
2
50
140
240
1.0
10
2
t
t
7
6
t
8
SET
= 560
Units
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
. All specifications T
Condition
50 MHz Grade
140 MHz Grade
240 MHz Grade
f
f
f
f
f
f
MIN
ADV7127
MAX
MAX
MAX
MAX
MAX
MAX
to T
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
MAX
3
unless

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