CS4382A-DQZR Cirrus Logic Inc, CS4382A-DQZR Datasheet - Page 37

• Manufacturer Part Number: CS4382A-DQZR
• Description: IC - 192kHz 6and8 Channel D/A Conv
• Manufacturer: Cirrus Logic Inc

Specifications of CS4382A-DQZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 680mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1524 - BOARD EVAL FOR CS4382A DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS618F2
6.3.6
6.4
6.4.1
6.4.2
6.4.3
Reserved
7
0
Filter Control (Address 04h)
Mutec Pin Control (MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’,
a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute
control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all
DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more in-
formation on the use of the mute control function see the MUTEC1 and MUTEC234 pins in
Interpolation Filter Select (FILT_SEL)
Default = 0
0 - Fast roll-off
1 - Slow roll-off
Function:
This function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter
characteristics, please see
De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µ s/50 µ s digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates. (see
De-emphasis is only available in Single-Speed Mode.
Soft Ramp-Down Before Filter Mode Change (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
If either the FILT_SEL or DEM bits are changed, the DAC will stop conversion for a period of time to
change filter values. This bit selects how the data is effected prior to and after the change of the filter val-
ues. When this bit is enabled, the DAC will ramp down the volume prior to a filter-mode change and ramp
Reserved
6
0
Reserved
5
0
Section
FILT_SEL
2.
4
0
Figure
Reserved
3
0
13)
DEM1
2
0
DEM0
1
0
CS4382A
Section
RMP_DN
0
0
5.
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