CS5511-ASZR Cirrus Logic Inc, CS5511-ASZR Datasheet
CS5511-ASZR
Specifications of CS5511-ASZR
Related parts for CS5511-ASZR
CS5511-ASZR Summary of contents
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... CS5510/12 provides better than simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscillator which eliminates the need for an ex- ternal clock source. Low-power, flexible supply configurations, compact pi- ...
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... Clock Generator ............................................................................................................... 14 2.4.1 External Clock Source for CS5510/12 ................................................................ 14 2.4.2 Internal Oscillator for CS5511/13 ........................................................................ 14 2.5 Performing Conversions .................................................................................................. 15 2.5.1 Reading Conversions - CS5510/12 ..................................................................... 16 2.5.2 Reading Conversions - CS5511/13 ..................................................................... 16 2.5.3 Output Coding ..................................................................................................... 17 2.5.4 Digital Filter ......................................................................................................... 18 2.5.5 Multiplexed Applications ...................................................................................... 19 2.6 Digital Off-chip System Calibration .................................................................................. 20 2.7 Power Consumption, Sleep and Reset ............................................................................ 20 2 ...
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... Figure 14. Typical Linearity Error for CS5510............................................................................... 15 Figure 15. Typical Linearity Error for CS5512............................................................................... 15 Figure 16. Data Word Timing for the CS5510............................................................................... 16 Figure 17. Data Word Timing for the CS5511............................................................................... 17 Figure 18. Data Word Timing for the CS5512............................................................................... 17 Figure 19. Data Word Timing for the CS5513............................................................................... 17 Figure 20. Digital Filter Response................................................................................................. 19 LIST OF TABLES Table 1 ...
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... Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° For peak-to-peak noise multiply by 6.6. 6. See the section of the data sheet which discusses Analog Input Models. 7. For CS5511/13, OWR = 107 Sps ± 50%. Specifications are subject to change without notice kHz ± ...
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... SDO. The voltage specified for SDO is relative to CS Figure 11 for more details. DS337F4 (Continued) (Note 8) 0.250 {(V+) - (V-)} (Note 9) CS5510 CS5511 CS5512 CS5513 CS5510 CS5511 CS5512 CS5513 (Note 10) CS5510 CS5511 CS5512 CS5513 (Note 11) and I may not always be the same value Symbol V CS and SCLK (Note 13 SCLK (Note 14) ...
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... Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 Symbol CS5510/ CS5511/ CS5510/12 OWR CS5511/13 OWR t s Symbol (Note 16) Positive V+ Negative V- (Notes 17 and 18 ...
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SWITCHING CHARACTERISTICS - CS5510/ 25° ±5 Input Levels: Logic Logic Parameter Master Clock Timing Master Clock Frequency (CS5510) Master Clock ...
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... Rates slower than this can potentially put the ADC into sleep as the sleep mode is entered after SCLK is logic 1 for t 25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held high (logic 1) for t or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must ...
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... t11 Figure 1. SDO Read Timing CS5510/12 (Not to Scale t11 Figure 2. SDO Read Timing CS5511/13 (Not to Scale). DS337F4 CS5510/11/12/ t10 ...
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... When configured with an external master clock of 32.768 kHz, the filter in the CS5510/12 provides better than simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscil- lator which eliminates the need for an external clock source. The CS5510/11/12/13 ADCs are designed to oper- ...
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CS5512/13. The CS5510/11 follow the same curve, but are limited to 16 bits of resolution. Note that the reference voltage should not be estab- lished prior to having the supply voltages on the V+ and V- pins. 2.2.1 Voltage Reference ...
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V Supply Differential Input (± 80% VREF) Common Mode = Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply. +2.5 V Supply Differential Input (± 80% VREF) Common Mode = -2.5 V ...
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V/+3.0V Supply Differential Input (± 80% VREF) Common Mode = -1.7 V/-2.0V Supply Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and +3.0 V and V- = -2.0 ...
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... ADCs. The CS5510/12 uses the SCLK input pin as its operating clock. The CS5511/13 has an on-chip oscillator that provides its master clock. The SCLK pin on the CS5511/13 is used only to read data and to put the part into sleep mode ...
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... VD Ω 32.768 kHz 47 pF Figure 12. External (CMOS Compatible) Clock CS5511/13 and oscillates at 64 kHz ±32 kHz. The output word rate (OWR) for the CS5511/13 is de- rived from the internal oscillator, and is equal to f /612. Due to the part-to-part variances in the osc oscillator frequency, the OWR of the CS5511/13 can vary between 53 Sps and 159 Sps ...
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... Reading Conversions - CS5511/13 After power-up, the CS5511/13 begins converting and updating the output register. When there is new data in the output register (at the end of a con- version cycle) the SDO line will fall to a logic-low level also at a logic-low state (SDO will al- ways be high-impedance when CS is high) ...
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... In the CS5510/11, there are four more bits of zero, and the remaining 16 bits are the conversion data, out- put MSB first (Table 2). In the CS5512/13, the final Figure 17. Data Word Timing for the CS5511 Figure 18. Data Word Timing for the CS5512 Figure 19 ...
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... The filter has a response as shown in Figure 20. Table 4 shows the filter re- sponse for frequencies from Hz. Note that the response of the CS5511/13 will be similar, but the frequencies scale with the on-chip oscilla- tor’s frequency, which can be from 32 kHz to 96 kHz (i.e. conversion rates can vary between 53 Sps to 159 Sps) ...
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... CS5510/12, switch- ing of a multiplexer should occur 595 SCLK cycles after SDO falls. For maximum throughput with the CS5511/13, switching of a multiplexer should oc- cur on the rising edge of SDO during a conversion in which the data word is not read. The conversion ...
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... In the 20-bit devices (CS5512 and CS5513), multiple conversions can be averaged to arrive at a more accurate offset val- ue. In the 16-bit devices (CS5510 and CS5511), averaging may not be meaningful, because the noise will be below the size of one LSB when using nominal voltages for VREF (2 ...
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... Schmitt trigger to allow for slow rise and fall time signals. If held high, the device will enter sleep mode. In the CS5510/12, this input is also used as a master clock source which determines conversion speeds and throughput. In the CS5511/13, SCLK is only used to read the conversion data and put the part in sleep mode. ...
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SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two end points of the A/D Converter transfer function. One end point is located 1/2 LSB below the first code transition and the ...
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... CS5510-ASZ External CS5511-ASZ Internal CS5512-BSZ External CS5513-BSZ Internal 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5510-ASZ CS5511-ASZ CS5512-BSZ CS5513-BSZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS337F4 Resolution Linearity Error (Max) Temperature Range ±0.003% 16 Bits ±0.0015% 20 Bits Peak Reflow Temp MSL Rating* 260 ° ...
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PACKAGE DIMENSIONS 8L SOIC (208 MIL BODY) PACKAGE DRAWING 1 b SEATING PLANE e DIM MIN A 0.076 A1 0.004 b 0.013 C 0.006 D 0.206 E 0.204 e 0.040 H 0.302 L 0.019 ∝ 0° ...
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REVISION HISTORY Revision Date F2 MAR 2005 Added lead-free (Pb) device ordering information. F3 AUG 2005 Updated lead-free (Pb) device ordering information. Added MSL data. F4 JUL 2009 Removed devices containing lead (Pb) from ordering information. DS337F4 CS5510/11/12/13 Changes ...
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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in ...