CS5512-BSZR Cirrus Logic Inc, CS5512-BSZR Datasheet
CS5512-BSZR
Specifications of CS5512-BSZR
Related parts for CS5512-BSZR
CS5512-BSZR Summary of contents
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... The CS5510/11/12/13 are low-cost, easy-to-use, ΔΣ an- alog-to-digital converters (ADCs) which use charge- balance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) performance. The ADCs are avail- able in a space-efficient, 8-pin SOIC package and are optimized for measuring signals in weigh scale, process control, and other industrial applications ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ANALOG CHARACTERISTICS ................................................................................................ 4 DIGITAL CHARACTERISTICS ................................................................................................. 5 DYNAMIC CHARACTERISTICS .............................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6 SWITCHING CHARACTERISTICS - CS5510/12 ..................................................................... 7 SWITCHING CHARACTERISTICS - CS5511/13 ..................................................................... 8 2. GENERAL ...
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... Figure 19. Data Word Timing for the CS5513............................................................................... 17 Figure 20. Digital Filter Response................................................................................................. 19 LIST OF TABLES Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits). ................. 18 Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). ................. 18 Table 3. CS5510/11/12/13 Output Coding. ................................................................................... 18 Table 4. Digital Filter Response at 32.768 kHz............................................................................ 19 ...
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... CS5510/12; OWR = 107 Sps ± 50% for CS5511/13) (See Note 1.) Parameter Accuracy Linearity Error (CS5510/11) Linearity Error (CS5512/13) No Missing Codes (CS5510/11) No Missing Codes (CS5512/13) Bipolar Offset (CS5510/11) Bipolar Offset (CS5512/13) Offset Drift Over Temperature Gain Drift Over Temperature Analog Input Common Mode + Signal on AIN+ or AIN- ...
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... SDO. The voltage specified for SDO is relative to CS Figure 11 for more details. DS337F4 (Continued) (Note 8) 0.250 {(V+) - (V-)} (Note 9) CS5510 CS5511 CS5512 CS5513 CS5510 CS5511 CS5512 CS5513 (Note 10) CS5510 CS5511 CS5512 CS5513 (Note 11) and I may not always be the same value Symbol V CS and SCLK (Note 13 SCLK (Note 14 SDO ...
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DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Frequency Output Word Rate Filter Settling Time to 1/2 LSB (Full Scale Step) ABSOLUTE MAXIMUM RATINGS ( (See Note 15.) Parameter DC Power Supplies Input Current, Any Pin Except Supplies Output Current ...
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... CS Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or 200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded linearity specifications, as shown in Figures 14 and 15. 21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. ...
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SWITCHING CHARACTERISTICS - CS5511/ 25° ±5 Input Levels: Logic Logic Parameter Internal Oscillator Timing Internal Oscillator Frequency Internal Oscillator Drift ...
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t11 Figure 1. SDO Read Timing CS5510/12 (Not to Scale t11 Figure 2. SDO ...
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... The CS5510/11/12/13 are low-cost, easy-to-use, ΔΣ analog-to-digital converters (ADCs) which use charge balance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) perfor- mance. The ADCs are available in a space-effi- cient, 8-pin, SOIC package and are optimized for measuring signals in weigh scale, process control, and other industrial applications ...
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... VREF (V) Figure 4. CS5512/13 Measured Noise-Free Bits vs. VREF. VREF ≤ DS337F4 nal reference. Typical CVF (sampling) current is about 6 nA (See Figure 5). The nominal input span of the converter is defined bipolar span equal to ±(VREF - V-)*(0.80 ± ...
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V Supply Differential Input (± 80% VREF) Common Mode = Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply. +2.5 V Supply Differential Input (± 80% VREF) Common Mode = -2.5 V ...
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V/+3.0V Supply Differential Input (± 80% VREF) Common Mode = -1.7 V/-2.0V Supply Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and +3.0 V and V- = -2.0 ...
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... Such a microcontroller circuit is shown in Figure 13. Note that the CS5510 can operate with an exter- nal, CMOS-compatible clock at frequencies up to 130 kHz, and the CS5512 can operate with an ex- ternal clock 200 kHz with a maximum jitter. Linearity performance is degraded slightly with higher clock speeds, as shown in Figures 14 and 15 ...
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... In the CS5511/13, SCLK is asynchronous to the on- chip oscillator and can be clocked at a rate MHz. 0.003 0.0025 0.002 0.0015 0.001 0.0005 90 110 130 Figure 15. Typical Linearity Error for CS5512. CS5510/11/12/13 Counter/Timer SCLK SDO µC CS OWR = SCLK 612 ...
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Reading Conversions - CS5510/12 After power-up, the CS5510/12 will begin convert- ing once a clock source is applied to the SCLK pin. When a conversion has completed, and there is new data in the output register, the SDO line ...
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... In the CS5510/11, there are four more bits of zero, and the remaining 16 bits are the conversion data, out- put MSB first (Table 2). In the CS5512/13, the final Figure 17. Data Word Timing for the CS5511. ...
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... The CS5510/11/12/13 have a modified Sinc tal filter that provides CLK/612 Hz conversion rates D23 D22 D21 D20 D11 D10 Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits). D23 D22 D21 D20 D11 D10 Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). ...
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Frequency Rejection Frequency (Hz) (dB) (Hz Table 4. Digital Filter Response at 32.768 kHz. ...
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... CS5510/11/12/13 will be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for the CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for the CS5512/13. The gain error (GE) is equal to: (Cr - ZP)/Ci. To correct for both offset and gain error in subsequent conversions, subtract the offset error, and then divide by the gain error. 2.7 ...
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PIN DESCRIPTIONS VREF AIN+ Control Pins and Serial Data I Chip Select, Pin dual function pin, which determines the state of SDO, as well as the digital logic-low output level. When CS is ...
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SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two end points of the A/D Converter transfer function. One end point is located 1/2 LSB below the first code transition and the ...
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... External CS5511-ASZ Internal CS5512-BSZ External CS5513-BSZ Internal 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5510-ASZ CS5511-ASZ CS5512-BSZ CS5513-BSZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS337F4 Resolution Linearity Error (Max) Temperature Range ±0.003% 16 Bits ±0.0015% 20 Bits Peak Reflow Temp MSL Rating* 260 ° ...
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PACKAGE DIMENSIONS 8L SOIC (208 MIL BODY) PACKAGE DRAWING 1 b SEATING PLANE e DIM MIN A 0.076 A1 0.004 b 0.013 C 0.006 D 0.206 E 0.204 e 0.040 H 0.302 L 0.019 ∝ 0° ...
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REVISION HISTORY Revision Date F2 MAR 2005 Added lead-free (Pb) device ordering information. F3 AUG 2005 Updated lead-free (Pb) device ordering information. Added MSL data. F4 JUL 2009 Removed devices containing lead (Pb) from ordering information. DS337F4 CS5510/11/12/13 Changes ...
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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in ...