CY62256VNLL-70SNXIT

Manufacturer Part NumberCY62256VNLL-70SNXIT
DescriptionCY62256VNLL-70SNXIT
ManufacturerCypress Semiconductor Corp
CY62256VNLL-70SNXIT datasheet
 


Specifications of CY62256VNLL-70SNXIT

Format - MemoryRAMMemory TypeSRAM
Memory Size256K (32K x 8)Speed70ns
InterfaceParallelVoltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CPackage / Case28-SOIC (7.5mm Width)
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Features
Temperature Ranges
Commercial: 0°C to 70°C
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
Automotive-E: –40°C to 125°C
Speed: 70 ns
Low Voltage Range: 2.7V to 3.6V
Low Active Power and Standby Power
Easy Memory Expansion with CE and OE Features
TTL Compatible Inputs and Outputs
Automatic Power Down when Deselected
CMOS for Optimum Speed and Power
Available in Standard Pb-free and non Pb-free 28-Pin (300-mil)
Narrow SOIC, 28-Pin TSOP-I, and 28-Pin Reverse TSOP-I
Packages
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
CE
WE
OE
.
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06512 Rev. *B
256K (32K x 8) Static RAM
Functional Description
The CY62256VN
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and tristate drivers.
These devices have an automatic power down feature, reducing
the power consumption by over 99% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
through I/O
0
by the address present on the address pins (A
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
INPUTBUFFER
32K x 8
ARRA Y
POWER
COLUMN
DOWN
DECODER
198 Champion Court
San Jose
CY62256VN
[1]
family is composed of two high performance
) is written into the memory location addressed
7
through A
0
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
,
CA 95134-1709
408-943-2600
Revised September 25, 2009
).
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CY62256VNLL-70SNXIT Summary of contents

  • Page 1

    ... Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 001-06512 Rev. *B 256K (32K x 8) Static RAM Functional Description The CY62256VN CMOS static RAM’s organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers ...

  • Page 2

    ... Product Portfolio Product Range CY62256VNLL Com’l CY62256VNLL Ind’l CY62256VNLL Automotive-A CY62256VNLL Automotive-E Pin Configurations Narrow SOIC Top View I I/O 4 I/O 3 GND 15 14 Pin Definitions Pin Number Type 1–10, 21, 23–26 Input A 0 11–13, 15–19 Input/Output ...

  • Page 3

    Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65° 150°C Ambient Temperature with Power Applied ........................................... –55° 125°C Supply Voltage to Ground ...

  • Page 4

    Capacitance [5] Parameter Description C Input Capacitance IN C Output Capacitance OUT [5] Thermal Resistance Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case OUTPUT 50 pF INCLUDING JIG AND ...

  • Page 5

    Switching Characteristics Over the Operating Range Parameter Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data Valid ...

  • Page 6

    Switching Waveforms ADDRESS DATA OUT PREVIOUS DATA VALID CE t ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT Figure 5. Write Cycle No. 1 (WE Controlled) ADDRESS ...

  • Page 7

    Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (CE Controlled) ADDRESS DATA I/O Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 17 t HZWE Document #: ...

  • Page 8

    Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 1.2 1.0 0 25°C 0.6 A 0.4 0.2 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 2.0 1 25°C A ...

  • Page 9

    ... High-Z Ordering Information Speed Ordering Code (ns) 70 CY62256VNLL-70SNC CY62256VNLL-70SNXC CY62256VNLL-70ZC CY62256VNLL-70ZXC CY62256VNLL-70SNXI CY62256VNLL-70ZI CY62256VNLL-70ZXI CY62256VNLL-70ZRI CY62256VNLL-70ZRXI CY62256VNLL-70ZXA CY62256VNLL-70SNXE CY62256VNLL-70ZXE CY62256VNLL-70ZRXE Contact your local Cypress sales representative for availability of other parts Document #: 001-06512 Rev. *B (continued) NORMALIZED I 1.25 1.00 0.75 0.50 1 800 1000 ...

  • Page 10

    Package Diagrams Figure 8. 28-Pin (300-mil) SNC (Narrow Body) (51-85092) Document #: 001-06512 Rev. *B CY62256VN 51-85092-*B Page [+] Feedback ...

  • Page 11

    Figure 9. 28-Pin TSOP 1 (8 × 13.4 mm) (51-85071) Document #: 001-06512 Rev. *B CY62256VN 51-85071-*G Page [+] Feedback ...

  • Page 12

    Figure 10. 28-Pin Reverse TSOP 1 (8 × 13.4 mm) (51-85074) Document #: 001-06512 Rev. *B CY62256VN 51-85074-*F Page [+] Feedback ...

  • Page 13

    ... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...