CY7C009V-20AXI Cypress Semiconductor Corp, CY7C009V-20AXI Datasheet
CY7C009V-20AXI
Specifications of CY7C009V-20AXI
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CY7C009V-20AXI Summary of contents
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... CY7C008V CY7C018V CY7C009V CY7C019V 3 K/128 K × 8/9 Dual-Port Static RAM 3 K/128 K × 8/9 Dual-Port Static RAM Features True dual-ported memory cells which allow simultaneous ■ access of the same memory location 64 K × 8 organization (CY7C008) ■ 128 K × 8 organization (CY7C009) ■ × 9 organization (CY7C018) ■ ...
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Functional Description The CY7C008V/009V and CY7C018V/019V are low-power CMOS 64 K, 128 K × 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports ...
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Contents Pin Configurations ........................................................... 4 Selection Guide ................................................................ 5 Pin Definitions .................................................................. 6 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 Electrical Characteristics ................................................. 7 Capacitance ...................................................................... 7 AC Test Loads and Waveforms ....................................... 8 Switching Characteristics ................................................ 8 Data ...
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... CE0L 18 CE1L 19 SEML 20 R/WL 21 OEL 22 GND Note 4. This pin is NC for CY7C008V. Document Number: 38-06044 Rev. *E Figure 1. 100-pin TQFP (Top View CY7C009V (128 K × 8) CY7C008V (64 K × CY7C008V/009V CY7C018V/019V A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R 65 A15R [4] 64 A16R 63 GND ...
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A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 A13L 9 A14L 10 A15L 11 [5] A16L 12 VCC ...
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... Supply voltage to ground potential ...............–0 +4 voltage applied to outputs in high Z State ......................... –0 Notes 6. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 7. Industrial parts are available in CY7C009V and CY7C019V only. Document Number: 38-06044 Rev. *E Description Chip enable (CE is LOW when CE Read/Write enable ...
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... Parameter Description C Input capacitance IN C Output capacitance OUT Notes 8. Industrial parts are available in CY7C009V and CY7C019V only 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level MAX RC RC standby I . SB3 10 ...
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AC Test Loads and Waveforms 3 590 OUTPUT 435 (a) Normal Load (Load 1) 3.0 V GND Switching Characteristics [11] Over the Operating Range Parameter Description READ CYCLE t ...
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Switching Characteristics [11] Over the Operating Range (continued) Parameter Description WRITE CYCLE t Write cycle time WC [16 LOW to write end SCE t Address valid to write end AW t Address hold from write end HA [16] ...
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Data Retention Mode The CY7C008V/009V and CY7C018V/019V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data ...
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Switching Waveforms Read Cycle No.1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No.2 (Either Port CE/OE Access DATA OUT CURRENT I SB [23, 25, 26, ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [32 R/W NOTE 34 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [32 R/W DATA IN Notes 28. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 40 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R Valid First ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...
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... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFFF (1FFFF for CY7C009V/19V R/W L INT R [43] t INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS WRITE FFFE (1FFFF for CY7C009V/19V R/W R INT L [43] t INS Right Side Clears INT ...
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Architecture The CY7C008V/009V and CY7C018V/019V consist of an array and 128 K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes 44. A and A , 1FFFF/1FFFE for the CY7C009V/19V. 0L–16L 0R–16R 45. If BUSY = L, then no change. R 46. If BUSY = L, then no change. ...
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... Ordering Information 128 K × 8 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C009V-15AXC 20 CY7C009V-20AXI 25 CY7C009V-25AXC Ordering Code Definitions Document Number: 38-06044 Rev. *E Package Name Package Type A100 100-pin Pb-free Thin Quad Flat Pack A100 100-pin Pb-free Thin Quad Flat Pack A100 100-pin Pb-free Thin Quad Flat Pack ...
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Package Diagram Figure 3. 100-pin Thin Plastic Quad Flat Pack (TQFP) A100 Document Number: 38-06044 Rev. *E CY7C008V/009V CY7C018V/019V 51-85048 *D Page [+] Feedback ...
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Acronyms Acronym Description CMOS complementary metal oxide semiconductor CE chip enable I/O input/output OE output enable SRAM static random access memory TQFP thin quad flat pack TTL Transistor–transistor logic WE write enable Document Number: 38-06044 Rev. *E CY7C008V/009V CY7C018V/019V Document ...
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... Change from Spec number: 38-00669 to 38-06044 Change pin 85 from BUSYL to BUSYR (pg. 3) Power up requirements added to Maximum Ratings Information Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI, CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC, CY7C019V-20AXI, CY7C019V-25AXC Removed inactive parts from ordering information table Updated package diagram ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...