CY7C1315BV18-250BZC Cypress Semiconductor Corp, CY7C1315BV18-250BZC Datasheet
CY7C1315BV18-250BZC
Specifications of CY7C1315BV18-250BZC
Available stocks
Related parts for CY7C1315BV18-250BZC
CY7C1315BV18-250BZC Summary of contents
Page 1
... Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311BV18) or 9-bit words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or 36-bit words (CY7C1315BV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and ...
Page 2
... Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 16 Reg. Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 18 Reg. CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 A (18:0) 19 RPS [7: (18:0) 19 RPS [8:0] 9 Page [+] Feedback ...
Page 3
... Logic Block Diagram (CY7C1313BV18) D [17:0] 18 Address Register A (17: CLK K Gen. DOFF V REF WPS Control BWS Logic [1:0] Logic Block Diagram (CY7C1315BV18) D [35:0] 36 Address Register A (16: CLK K Gen. DOFF V REF WPS Control Logic BWS [3:0] Document Number: 38-05620 Rev. *C Write Write Write ...
Page 4
... V DDQ CY7C1911BV18 ( WPS NC K NC/144M A NC/288M K BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 NC/36M CQ RPS DDQ DDQ DDQ DDQ DDQ REF DDQ DDQ DDQ TMS TDI RPS A NC/36M DDQ DDQ DDQ DDQ DDQ REF DDQ DDQ ...
Page 5
... D35 Q26 R TDO TCK A Document Number: 38-05620 Rev. *C CY7C1313BV18 ( WPS BWS K NC/288M BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1315BV18 (512K x 36 WPS BWS K BWS BWS BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 9 10 ...
Page 6
... CY7C1311BV18 arrays each of 512K x 9) for CY7C1911BV18, arrays each of 256K x 18) for CY7C1313BV18 and 512K arrays each of 128K x 36) for CY7C1315BV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311BV18 and CY7C1911BV18, 18 address inputs for CY7C1313BV18 and 17 address inputs for CY7C1315BV18 ...
Page 7
... Power Supply Power supply inputs for the outputs of the device. DDQ Functional Overview The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, CY7C1315BV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port ...
Page 8
... QDR-II. In the single clock mode generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 with , Page [+] Feedback ...
Page 9
... Vddq [9] D( ↑ ↑ ↑ ↑ Q( ↑ ↑ Q C(t + 2)↑ ↑ High High-Z Previous State Previous State ↑ represents rising edge. CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 SRAM # 250ohms CQ/CQ High High-Z Previous State Previous State ...
Page 10
... Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document Number: 38-05620 Rev. *C CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 [2, 10] Comments ) are written into the device, [7:0] ) are written into the device. ...
Page 11
... D will remain unaltered. [26:0] into the device. D will remain unaltered. [26:0] – No data is written into the device during this portion of a write operation. [2, 10] CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 ) are written [35:0] ) are written [35: written [8: written [8: written into [17: written into ...
Page 12
... It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Page [+] Feedback ...
Page 13
... Document Number: 38-05620 Rev. *C CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The ...
Page 14
... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 38-05620 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
Page 15
... OL = 100 µ GND ≤ V ≤ [13, 14] Over the Operating Range Description / ns − /2), Undershoot: V (AC) > 1.5V (Pulse width less than t CYC IL CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Selection TDO Circuitry Min. Max. Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD µA – ...
Page 16
... Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document Number: 38-05620 Rev. *C [13, 14] Over the Operating Range (continued) Description [14] ALL INPUT PULSES 1. TCYC t TMSS t TMSH t TDIS t TDIH t TDOV t TDOX CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Min. Max. Unit 0.9V Page [+] Feedback ...
Page 17
... Do Not Use: This instruction is reserved for future use. 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 CY7C1315BV18 Description 000 Version number. type of SRAM. 00000110100 Allows unique identification of SRAM vendor. ...
Page 18
... Bit # Bump ID 11H 54 7B 10G 11F 57 5B 11G 10F 60 5C 11E 61 4B 10E 62 3A 10D 10C 65 2B 11D 11B 69 3D 11C 10B 72 2C 11A 73 3E Internal CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Bit # Bump 100 1P 101 3R 102 4R 103 4P 104 5P 105 5N 106 5R Page [+] Feedback ...
Page 19
... If the input clock is unstable and the DLL is enabled, then the DLL may lock to an incorrect frequency, causing unstable SRAM behavior REF > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tied to V DDQ ) CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Start Normal Operation Page [+] Feedback ...
Page 20
... V REF Test Conditions T = 25° MHz 1. 1.5V DDQ (min.) within 200 ms. During this time V < V and DDQ (Max.) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 [21] [21 DDQ 1.8 ± 0.1V 1. Typ. Max. Unit 1.7 1.8 1.9 V 1.4 1 0.12 ...
Page 21
... REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω (b) /I and load capacitance shown in ( Test Loads CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 165 FBGA Package Unit 28.51 °C/W 5.91 °C/W [24] ALL INPUT PULSES 1.25V 0.75V Slew Rate = 2 V/ns = 1.5V, input DDQ Page [+] Feedback ...
Page 22
... V is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies. CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 200 MHz 167 MHz Unit 5.25 5.0 6.3 6.0 8 ...
Page 23
... CLZ CHZ CO CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 200 MHz 167 MHz Unit – –0.45 – –0.50 – ns 0.30 – 0.35 – 0.40 ns – –0.35 – –0.40 – ns 0.45 – ...
Page 24
... WRITE READ WRITE KHKH D12 D13 D10 D11 Q00 Q01 Q02 Q03 CLZ t DOH t KHKH t CCQO t CQOH t CCQO t CQOH DON’T CARE CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 NOP D30 D31 D32 D33 Q20 Q21 Q22 Q23 t CHZ t CQDOH t CQD UNDEFINED Page [+] Feedback ...
Page 25
... Fine Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1911BV18-200BZXI CY7C1313BV18-200BZXI CY7C1315BV18-200BZXI 250 CY7C1311BV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1911BV18-250BZC CY7C1313BV18-250BZC CY7C1315BV18-250BZC CY7C1311BV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1911BV18-250BZXC CY7C1313BV18-250BZXC CY7C1315BV18-250BZXC Document Number: 38-05620 Rev. *C CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 for actual products offered ...
Page 26
... Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1911BV18-300BZC CY7C1313BV18-300BZC CY7C1315BV18-300BZC CY7C1311BV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1911BV18-300BZXC CY7C1313BV18-300BZXC CY7C1315BV18-300BZXC CY7C1311BV18-300BZI 51-85180 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1911BV18-300BZI CY7C1313BV18-300BZI CY7C1315BV18-300BZI CY7C1311BV18-300BZXI 51-85180 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Lead-Free ...
Page 27
... SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø0. Ø0. -0.06 Ø ...
Page 28
... Document History Page Document Title: CY7C1311BV18/CY7C1911BV18/CY7C1313BV18/CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Document Number: 38-05620 Orig. of REV. ECN No. Issue Date Change ** 252474 See ECN SYT *A 325581 See ECN SYT *B 413997 See ECN NXR *C 472384 See ECN NXR Document Number: 38-05620 Rev. *C ...