CY7C1315CV18-250BZI Cypress Semiconductor Corp, CY7C1315CV18-250BZI Datasheet

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... DDR interfaces. Each address location is associated with four 8-bit words (CY7C1311CV18) or 9-bit words (CY7C1911CV18) or 18-bit words (CY7C1313CV18) or 36-bit words (CY7C1315CV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C ...

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... D [8:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 16 Reg. Write Write ...

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... Logic Block Diagram (CY7C1313CV18 [17:0] 18 Address A (17:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1315CV18 [35:0] 17 Address A (16:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 ...

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... Pin Configuration The pin configuration for CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 follow NC/72M DOFF V V REF DDQ TDO TCK NC/72M DOFF V V REF DDQ TDO TCK A Note 1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level. ...

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... Pin Configuration (continued) The pin configuration for CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 follow NC/144M NC/36M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO ...

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... CY7C1311CV18 arrays each of 512K x 9) for CY7C1911CV18, arrays each of 256K x 18) for CY7C1313CV18 and 512K arrays each of 128K x 36) for CY7C1315CV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311CV18 and CY7C1911CV18, 18 address inputs for CY7C1313CV18 and 17 address inputs for CY7C1315CV18 ...

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... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Pin Description Switching Characteristics on page 24. Switching Characteristics on page 24. output impedance are set to 0.2 x RQ, where resistor connected [x:0] ...

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... Functional Overview The CY7C1311CV18, CY7C1911CV18, CY7C1315CV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port ...

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... All pending transactions (read and write) are completed before the device is deselected. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow the SRAM to adjust its output SS driver impedance ...

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... MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed 50ohms Truth Table The truth table for CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 follows. Operation K RPS WPS [8] Write Cycle: L-H H Load address on the rising edge of K; write data on two consecutive K and K rising edges. [9] ...

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... Note 10. Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 [2, 10] Comments ) are written into the device, [7:0] ) are written into the device ...

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... Write Cycle Descriptions The write cycle description table for CY7C1315CV18 follows. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 [2, 10] K Comments – During the data portion of a write sequence, all four bytes (D the device. L– ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 16 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 [11] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 13. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 14. All Voltage referenced to Ground. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 0 Bypass Register Instruction Register ...

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... CS CH 16. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Description [16] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Value CY7C1911CV18 CY7C1313CV18 000 000 00000110100 00000110100 ...

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... Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 1H 10D 10C 66 3B 11D ...

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... DDQ DOFF Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...

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... V REF DDQ 21. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch-up Current ................................................... > 200 mA Operating Range Range Commercial ...

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... I Automatic Power Down SB1 Current AC Electrical Characteristics [13] Over the Operating Range Parameter Description V Input HIGH Voltage IH V Input LOW Voltage IL Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Test Conditions V = Max, 200 MHz (x8 mA, OUT (x9 1/t MAX CYC (x18) (x36) 167 MHz ...

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... Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Test Conditions T = 25° MHz ...

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... This part has a voltage regulator internally; t POWER initiated. 25. For D2 data signal on CY7C1911CV18 device, t Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max [24 ...

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... CHZ CLZ 28. At any voltage and temperature t is less than t CHZ Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max – 0.45 – 0.45 – ...

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... Outputs are disabled (High-Z) one clock cycle after a NOP. 31. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 [29, 30, 31] WRITE READ WRITE ...

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... CY7C1311CV18-278BZXI CY7C1911CV18-278BZXI CY7C1313CV18-278BZXI CY7C1315CV18-278BZXI Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...

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... Speed (MHz) Ordering Code 250 CY7C1311CV18-250BZC CY7C1911CV18-250BZC CY7C1313CV18-250BZC CY7C1315CV18-250BZC CY7C1311CV18-250BZXC CY7C1911CV18-250BZXC CY7C1313CV18-250BZXC CY7C1315CV18-250BZXC CY7C1311CV18-250BZI CY7C1911CV18-250BZI CY7C1313CV18-250BZI CY7C1315CV18-250BZI CY7C1311CV18-250BZXI CY7C1911CV18-250BZXI CY7C1313CV18-250BZXI CY7C1315CV18-250BZXI 200 CY7C1311CV18-200BZC CY7C1911CV18-200BZC CY7C1313CV18-200BZC CY7C1315CV18-200BZC CY7C1311CV18-200BZXC CY7C1911CV18-200BZXC CY7C1313CV18-200BZXC CY7C1315CV18-200BZXC CY7C1311CV18-200BZI CY7C1911CV18-200BZI CY7C1313CV18-200BZI CY7C1315CV18-200BZI CY7C1311CV18-200BZXI ...

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... CY7C1311CV18-167BZXI CY7C1911CV18-167BZXI CY7C1313CV18-167BZXI CY7C1315CV18-167BZXI Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...

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... Package Diagram Figure 6. 165-Ball FBGA ( 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document Number: 001-07165 Rev. *D CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 0.15(4X) BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. -0.06 Ø0.50 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...

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... Document History Page Document Title: CY7C1311CV18/CY7C1911CV18/CY7C1313CV18/CY7C1315CV18, 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Document Number: 001-07165 Submission Orig. of Rev. ECN No. Date Change ** 433284 See ECN NXR *A 462615 See ECN NXR *B 850381 See ECN VKN *C 1523386 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated I ...