CY7C1315KV18-250BZC Cypress Semiconductor Corp, CY7C1315KV18-250BZC Datasheet

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CY7C1315KV18-250BZC

Manufacturer Part Number
CY7C1315KV18-250BZC
Description
CY7C1315KV18-250BZC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1315KV18-250BZC

Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
18M (512K x 36)
Speed
250MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Quantity
Price
Part Number:
CY7C1315KV18-250BZC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1315KV18-250BZC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY7C1315KV18-250BZCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
18-Mbit QDR
Features
Selection Guide
Cypress Semiconductor Corporation
Document Number: 001-58904 Rev. *C
Maximum operating frequency
Maximum operating current
Separate independent read and write data ports
333-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
Two Input Clocks for Output Data (C and C) to minimize Clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in ×8, ×9, ×18, and ×36 configurations
Full data coherency, providing most current data
Core V
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
PLL for accurate data placement
®
II SRAM Four-Word Burst Architecture
Supports concurrent transactions
SRAM uses rising edges only
Supports both 1.5 V and 1.8 V I/O supply
®
DD
II operates with 1.5 cycle read latency when DOFF is
= 1.8 V (±0.1 V); I/O V
Description
DDQ
× 18
× 36
× 8
× 9
= 1.4 V to V
333 MHz
333
520
520
530
730
198 Champion Court
DD
300 MHz
300
490
490
500
670
Configurations
CY7C1311KV18 – 2 M × 8
CY7C1911KV18 – 2 M × 9
CY7C1313KV18 – 1 M × 18
CY7C1315KV18 – 512 K × 36
Functional Description
The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and
CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs,
equipped with QDR II architecture. QDR II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR II architecture has
separate data inputs and data outputs to completely eliminate
the need to ‘turnaround’ the data bus that exists with common
I/O devices. Each port can be accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR II read and write ports are independent of one
another. To maximize data throughput, both read and write ports
are equipped with DDR interfaces. Each address location is
associated with four 8-bit words (CY7C1311KV18), 9-bit words
(CY7C1911KV18), 18-bit words (CY7C1313KV18), or 36-bit
words (CY7C1315KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus ‘turnarounds’.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Four-Word Burst Architecture
250 MHz
CY7C1313KV18, CY7C1315KV18
CY7C1311KV18, CY7C1911KV18
250
430
430
440
590
San Jose
18-Mbit QDR
,
CA 95134-1709
200 MHz
200
380
380
390
500
167 MHz
Revised March 1, 2011
®
167
340
340
350
450
II SRAM
408-943-2600
MHz
Unit
mA
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Related parts for CY7C1315KV18-250BZC

CY7C1315KV18-250BZC Summary of contents

Page 1

... DDR interfaces. Each address location is associated with four 8-bit words (CY7C1311KV18), 9-bit words (CY7C1911KV18), 18-bit words (CY7C1313KV18), or 36-bit words (CY7C1315KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus ‘ ...

Page 2

... D [8:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 16 Reg. Write Write ...

Page 3

... Logic Block Diagram (CY7C1313KV18 [17:0] 18 Address A (17:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1315KV18 [35:0] 17 Address A (16:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 ...

Page 4

... TAP Instruction Set ................................................... 14 TAP Controller State Diagram ....................................... 16 TAP Controller Block Diagram ...................................... 17 TAP Electrical Characteristics ...................................... 17 Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 TAP AC Switching Characteristics ............................... 18 TAP Timing and Test Conditions .................................. 18 Identification Register Definitions ................................ 19 Scan Register Sizes ....................................................... 19 Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Power Up Sequence in QDR II SRAM ...

Page 5

... Pin Configuration The pin configurations for CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 follow NC/72M DOFF V V REF DDQ TDO TCK NC/72M DOFF V V REF DDQ TDO TCK A Note 1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level. ...

Page 6

... Pin Configuration (continued) The pin configurations for CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 follow NC/144M NC/36M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO ...

Page 7

... M × arrays each of 512 K × 8) for CY7C1311KV18 × arrays each of 512 K × 9) for CY7C1911KV18 × arrays each of 256 K × 18) for CY7C1313KV18 and 512 K × arrays each of 128 K × 36) for CY7C1315KV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311KV18 and CY7C1911KV18, 18 address inputs for CY7C1313KV18 and 17 address inputs for CY7C1315KV18 ...

Page 8

... Ground for the Device Power supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Pin Description Switching Characteristics on page output impedance are set to 0.2 x RQ, where resistor connected [x:0] 26. , which enables the ...

Page 9

... Functional Overview The CY7C1311KV18, CY7C1911KV18, CY7C1315KV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port ...

Page 10

... The value of RQ must be 5 × the value of the intended line impedance driven by the SRAM, the allowable Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 range guarantee impedance matching with a tolerance of ±15% is between 175  and 350  with V ...

Page 11

... BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed 50ohms Truth Table The truth table for CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 follow. Operation K RPS WPS [8] Write cycle: L–H H Load address on the rising edge of K; input write data on two consecutive K and K rising edges. ...

Page 12

... Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Comments ) are written into the device. [7:0] ) are written into the device. ...

Page 13

... Write Cycle Descriptions The write cycle description table for CY7C1315KV18 follows. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Notes 12 ‘Don't Care’ Logic HIGH Logic LOW, 13. Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved ...

Page 14

... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 17 ...

Page 15

... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

Page 16

... The state diagram for the TAP controller follows. Test-Logic 1 Reset 0 1 Test-Logic/ 0 Idle Note 14. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 [14] 1 Select DR-Scan 0 1 Capture- Shift- ...

Page 17

... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 16. Overshoot: V (AC) < 0.85 V (Pulse width less than t IH DDQ 17. All voltage referenced to Ground. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 0 Bypass Register Instruction Register ...

Page 18

... CS CH 19. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Description [19] Figure 2. TAP Timing and Test Conditions 0  ...

Page 19

... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Value CY7C1911KV18 CY7C1313KV18 000 000 00000110100 00000110100 ...

Page 20

... Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 1H 10D 10C 66 3B 11D ...

Page 21

... DDQ DOFF Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 PLL Constraints PLL uses K clock as its synchronizing input. The input must ■ have low phase jitter, which is specified as t The PLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the PLL is enabled, then the ■ ...

Page 22

... RQ <= 350 ohms. OL DDQ 25. V (min whichever is larger, V REF DDQ Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Neutron Soft Error Immunity Parameter LSBU LMBU DD + 0.3 V DDQ + 0 SEL * No LMBU or SEL events occurred during testing; this column represents a 2 statistical  ...

Page 23

... Over the Operating Range Parameter Description [26 operating supply DD DD Note 26. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Test Conditions V = Max mA, 333 MHz (× OUT 1/t MAX CYC (× 9) (× ...

Page 24

... Over the Operating Range Parameter Description V Input HIGH voltage IH V Input LOW voltage IL Note 27. Overshoot: V (AC) < 0.85 V (Pulse width less than t IH DDQ Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Test Conditions Max V , 333 MHz (× Both ports deselected, (× 9)  V  V  ...

Page 25

... Note 28. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0. 250 , V pulse levels of 0. 1.25 V, and output loading of the specified I Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Test Conditions = 25  MHz 1 ...

Page 26

... When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range. 31. This part has a voltage regulator internally; t POWER Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 333 MHz 300 MHz Min Max Min Max Min Max Min Max Min Max [31] 1 – ...

Page 27

... For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock µs (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 333 MHz 300 MHz Min Max Min Max Min Max Min Max Min Max – ...

Page 28

... Outputs are disabled (High Z) one clock cycle after a NOP. 38. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 [36, 37, 38] WRITE READ WRITE ...

Page 29

... Table 1. Ordering Information Speed (MHz) Ordering Code 333 CY7C1911KV18-333BZC CY7C1313KV18-333BZC CY7C1315KV18-333BZC 300 CY7C1911KV18-300BZC CY7C1315KV18-300BZC CY7C1911KV18-300BZXC CY7C1315KV18-300BZXC 250 CY7C1911KV18-250BZC CY7C1313KV18-250BZC CY7C1315KV18-250BZC CY7C1911KV18-250BZXC CY7C1315KV18-250BZXC CY7C1313KV18-250BZI CY7C1315KV18-250BZI CY7C1313KV18-250BZXI CY7C1315KV18-250BZXI Ordering Code Definitions CY 7C XXXX K V18 - XXX BZ X Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 www ...

Page 30

... Package Diagram Figure 6. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 0.15(4X) BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø0.50 -0.06 (165X) +0. 1.00 5.00 10.00 B 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...

Page 31

... TAP test access port TCK test clock TMS test mode select TDI test data-in TDO test data-out Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Document Conventions Units of Measure Symbol Unit of Measure µs micro seconds ns nano seconds  ohms K kilo ohms ...

Page 32

... Document History Page Document Title: CY7C1311KV18/CY7C1911KV18/CY7C1313KV18/CY7C1315KV18, 18-Mbit QDR Architecture Document Number: 001-58904 Orig. of Submission Rev. ECN No. Change Date ** 2860800 VKN 01/20/2010 *A 2897083 AJU 03/22/10 *B 3076901 NJY 11/03/2010 *C 3167511 NJY 02/09/2011 Document Number: 001-58904 Rev. *C CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 Description of change New datasheet Removed inactive parts Changed status from Preliminary to Final ...

Page 33

... QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 cypress.com/go/plc Revised March 1, 2011 PSoC Solutions psoc ...

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