CY7C4225-15ASXC Cypress Semiconductor Corp, CY7C4225-15ASXC Datasheet
CY7C4225-15ASXC
Specifications of CY7C4225-15ASXC
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CY7C4225-15ASXC Summary of contents
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... Features ■ High speed, low power, first-in first-out (FIFO) memories ■ (CY7C4425) ■ 256 x 18 (CY7C4205) ■ 512 x 18 (CY7C4215) ■ (CY7C4225) ■ (CY7C4235) ■ (CY7C4245) ■ High speed 100 MHz operation (10 ns read/write cycle time) ■ Low power ( mA) CC ■ ...
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... D 35 GND 2728 2930 CY7C4425/4205/4215 CY7C4225/4235/4245 FLAG PROGRAM REGISTER FF EF FLAG PAE LOGIC PAF SMODE READ POINTER READ CONTROL RCLK REN Figure 2. PLCC (Top View /SMODE GND CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 51 GND Q 50 CY7C4245 GND 3132 3940 4142 43 Page [+] Feedback ...
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... FL tied tied all devices. Not Cascaded – Tied available in standalone mode by strobing RT. Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to V Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to V CY7C4425/4205/4215 CY7C4225/4235/4245 -15 -25 - ...
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... ENS before LD WEN ENS 0 0 0–17 outputs 0− outputs even 0− CY7C4425/4205/4215 CY7C4225/4235/4245 Function . CC . (Almost Empty synchro- SS during a program write will determine the 0–11 Table 2). When the Table 1). Writing all [1] WCLK Selection Writing to offset registers: Empty Offset Full Offset No Operation Write Into FIFO ...
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... Note Empty Offset (Default Values: CY7C4425 CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127 Full Offset (Default Values: CY7C4425 CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127). Document Number: 001-45652 Rev. *A that the FIFO is either Almost Full or Almost Empty. See for a description of programmable flags. ...
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... CY7C42X5. RESET (RS) 18 7C4425 7C4205 7C4425 7C4215 7C4205 7C4225 7C4215 7C4235 7C4225 7C4245 7C4235 7C4245 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) CY7C4425/4205/4215 CY7C4225/4235/4245 Figure 3 READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE(OE) PROGRAMMABLE(PAF) EMPTYFLAG (EF) EF DATAOUT ( Page [+] Feedback ...
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... V CC 7C4245 FF EF PAE PAF WXI RXI READ CLOCK (RCLK) WXO RXO READ ENABLE (REN) 7C4425 7C4205 OUTPUT ENABLE (OE) 7C4215 7C4225 7C4235 7C4245 FF EF PAE PAF WXI RXI CY7C4425/4205/4215 CY7C4225/4235/4245 DATAOUT (Q) EF PAE 42X5–23 Page [+] Feedback ...
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... IH < V < Max., Com’ Ind’ Max., Com’ Ind’l 15 Test Conditions ° MHz 5.0V CC CY7C4425/4205/4215 CY7C4225/4235/4245 Ambient Temperature V CC ° ° + ± 10% ° ° ± 10% -15 -25 -35 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0 ...
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... Vth = 1.91V -10 Min. Max. 100 4.5 4.5 3 0 [16 [16 [17] 12 /SMODE tied /SMODE tied [17] 12 /SMODE tied /SMODE tied OHZ . PAF(E) CY7C4425/4205/4215 CY7C4225/4235/4245 [13, 14] ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ -15 -25 -35 Min. Max. Min. Max. Min. Max. 66 ...
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... Document Number: 001-45652 Rev. *A -10 -15 Min. Max. Min 6.5 4 Figure 6. Write Cycle Timing t CLK t CLKL ENH t ENS t WFF , then FF may not change state until the next WCLK edge. SKEW1 CY7C4425/4205/4215 CY7C4225/4235/4245 -25 -35 Max. Min. Max. Min. Max. Unit OPERATION Page [+] Feedback ...
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... Document Number: 001-45652 Rev. *A Figure 7. Read Cycle Timing t CLK t CLKH CLKL NO OPERATION t REF t A VALID DATA t OE [19] t SKEW2 [20] Figure 8. Reset Timing RSR t RSF t RSF t RSF , then EF may not change state until the next RCLK edge. SKEW2 CY7C4425/4205/4215 CY7C4225/4235/4245 t REF t OHZ [21 Page [+] Feedback ...
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... The first word is available the cycle after EF goes HIGH, always. Document Number: 001-45652 Rev [22] t FRL t REF OLZ t OE Figure 10. Empty Flag Timing ENS t t REF REF When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4425/4205/4215 CY7C4225/4235/4245 [23 ENH t [22] FRL t t REF SKEW2 D0 (maximum) = either 2 FRL CLK SKEW2 CLK Page [+] Feedback ...
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... Document Number: 001-45652 Rev. *A Figure 11. Full Flag Timing [18 SKEW1 DATA WRITE t WFF t ENS DATAREAD Figure 12. Half-Full Flag Timing t CLKL t t ENS ENH t HF HALF FULL+1 OR MORE t ENS CY7C4425/4205/4215 CY7C4225/4235/4245 NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ HALF FULL OR LESS t HF Page [+] Feedback ...
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... If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. Document Number: 001-45652 Rev CLKL t t ENS ENH t PAE t ENS t CLKL t t ENS ENH Note 25 [26] t PAEsynch t ENS CY7C4425/4205/4215 CY7C4225/4235/4245 n+1 WORDS n WORDS IN FIFO IN FIFO t PAE WORDS Note 27 INFIFO t PAEsynch t t ENS ENH Page [+] Feedback ...
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... CY7C4425, 256 – m words in CY7C4205, 512 − m words in CY7C4215. 1024 – m words in CY7C4225, 2048 − m words in CY7C4235, and 4096 – m words in CY7C4245. 31. 64 − words in CY7C4425, 256 − words in CY7C4205, 512 − words in CY7C4215, 1024 − CY7C4225, 2048 − CY7C4235, and 4096 − words in CY7C4245. ...
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... Document Number: 001-45652 Rev. *A Figure 17. Write Programmable Registers t CLKL t ENH t DH PAE OFFSET PAF OFFSET Figure 18. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET Figure 19. Write Expansion Out Timing Note CY7C4425/4205/4215 CY7C4225/4235/4245 PAE OFFSET D – PAF OFFSET PAE OFFSET Page [+] Feedback ...
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... For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document Number: 001-45652 Rev. *A Figure 20. Read Expansion Out Timing Note Figure 21. Write Expansion In Timing XIS Figure 22. Read Expansion In Timing [37, 38, 39] Figure 23. Retransmit Timing t PRT to update these flags. RTR CY7C4425/4205/4215 CY7C4225/4235/4245 XIS t RTR . RTR Page [+] Feedback ...
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... AMBIENT TEMPERATURE (°C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 120 140 120 100 T =25° =5. OUTPUT VOLTAGE (V) CY7C4425/4205/4215 CY7C4225/4235/4245 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.1 V =5. =25°C A 1.0 V =3.0V IN 0.9 0.8 0.7 0.6 125 100 FREQUENCY (MHz) TYPICAL t CHANGE vs. A OUTPUT LOADING ...
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... Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4205-10AXC 512 x 18 Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4215-15AXI Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4225-10AXI 15 CY7C4225-15AXC CY7C4225-15ASXC Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4245-10AXI 15 CY7C4245-15AXC CY7C4245-15ASXC Ordering Code Definitions Document Number: 001-45652 Rev. *A Package Name ...
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... Package Diagrams Figure 25. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85046 Document Number: 001-45652 Rev. *A CY7C4425/4205/4215 CY7C4225/4235/4245 51-85046 *D Page [+] Feedback ...
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... Package Diagrams (continued) Figure 26. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm), 51-85051 Figure 27. 68-Pin Plastic Leaded Chip Carrier, 51-85005 Document Number: 001-45652 Rev. *A CY7C4425/4205/4215 CY7C4225/4235/4245 51-85051 *B 51-85005 *B Page [+] Feedback ...
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... Document History Page Document Title: CY7C4425/CY7C4205/CY7C4215/CY7C4225/CY7C4235/CY7C4245, 64/256/512/1K/2K/ Synchronous FIFOs Document Number: 001-45652 REV. ECN NO. Issue Date ** 2489087 See ECN *A 3094407 11/24/10 © Cypress Semiconductor Corporation, 2008-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...