CY7C4255V-15ASXC Cypress Semiconductor Corp, CY7C4255V-15ASXC Datasheet
CY7C4255V-15ASXC
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CY7C4255V-15ASXC Summary of contents
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... K/64 K × 18 Low Voltage Deep Sync FIFOs Features 3.3 V operation for low power consumption and easy integration ■ into low voltage systems High speed, low power, first-in first-out (FIFO) memories ■ × 18 (CY7C4255V) ■ × 18 (CY7C4265V) ■ × 18 (CY7C4275V) ■ × 18 (CY7C4285V) ■ ...
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... High Density Dual-Port RAM Array 8Kx9 16Kx9 32Kx9 WRITE 64Kx9 POINTER RESET LOGIC THREE-ST ATE OUTPUT REGISTER LOGIC – 17 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V CY7C4275V CY7C4285V 64 K × 18 64-pin 10×10 TQFP FLAG PROGRAM REGISTER FF EF FLAG PAE LOGIC PAF SMODE READ POINTER ...
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... Programmable Almost Empty/Almost Full Flag ........... 7 Retransmit ......................................................................... 7 Width Expansion Configuration ...................................... 7 Depth Expansion Configuration (with Programmable Flags) ............................................. 8 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 Document Number: 38-06012 Rev. *D CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Electrical Characteristics ............................................... 10 Capacitance .................................................................... 10 Switching Characteristics .............................................. 12 Switching Waveforms .................................................... 13 Ordering Information ...................................................... 21 Ordering Code Definitions ......................................... 21 Package Diagram ............................................................ 22 Acronyms ...
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... Pinouts Document Number: 38-06012 Rev. *D Figure 1. Pin Diagram - 64-pin STQFP Top View CY7C4255V 42 7 CY7C4265V CY7C4275V CY7C4285V CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V GND GND GND 4275V–3 Page [+] Feedback ...
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... OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V /SMODE is tied ...
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... EF is LOW, regardless of the state of REN synchronized to RCLK, that is outputs even exclusively updated by each rising edge of RCLK. 0–17 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V during a program write 0–15 7). When the Load LD pin is set LOW and WEN is written into the Empty 0– ...
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... FIFO can be repeatedly retransmitted. Notes Empty Offset (Default Values: CY7C4255/65/75/85V n = 127 Full Offset (Default Values: CY7C4255/65/75/85V n = 127). Document Number: 38-06012 Rev. *D CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V the flags have been programmed, the PAF or PAE is asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 3 for a description of programmable flags ...
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... RESET (RS) 18 7C4255V 7C4255V 7C4265V 7C4265V 7C4275V 7C4275V 7C4285V 7C4285V FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF) EMPTY FLAG (EF) EF DATA OUT ( 4275V–24 Page [+] Feedback ...
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... PAF PAE WXI RXI READ CLOCK (RCLK) WXO RXO READ ENABLE (REN) 7C4255V 7C4265V OUTPUT ENABLE (OE) 7C4275V 7C4285V FF EF PAE PAF WXI RXI FIRST LOAD (FL) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V DATA OUT (Q) EF PAE 4275V–25 Page [+] Feedback ...
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... CC OL 2.0 –0 Max – < V < V – Commercial Industrial Commercial Industrial Test Conditions ° MHz 3 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V [5] AmbientTemperature °C to +70 °C 3.3 V ± 300 mV –40 °C to +85 °C 3.3 V ± 300 mV 7C4255/65/75/85V-15 Unit Max Min Max 2.4 V 0 0.8 – ...
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... Equivalent to: THÉ VENIN EQUIVALENT OUTPUT Figure 5. AC Test Loads and Waveforms (–10 3.0 V GND 4275V–6 . CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V [12, 13] ALL INPUT PULSES 90% 90% 10% 10% 4287V–5 200 2.0 V ALL INPUT PULSES 90% ...
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... Values guaranteed by design, not currently tested. 16 after program register write are valid until PAFasynch PAEasynch Document Number: 38-06012 Rev. *D 7C4255/85V-10 Min 2 10 4.5 4.5 3 [15] 3 [15] 3 [16 [16 4 PAF(E) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 7C4255/65/75/85V-15 Unit Max Min Max 100 66.7 MHz ...
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... NO OPERATION t REF VALID DATA t OE [18] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V NO OPERATION t WFF REF t OHZ Page [+] Feedback ...
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... The first word is always available the cycle after EF goes HIGH. Document Number: 38-06012 Rev. *D [19] Figure 8. Reset Timing RSR t RSF t RSF t RSF [21] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V [20] OE=1 OE [22 (maximum) = either 2 × FRL CLK SKEW2 Page [+] Feedback ...
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... RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between SKEW1 the rising edge of RCLK and the rising edge of WCLK is less than t Document Number: 38-06012 Rev. *D CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Figure 10. Empty Flag Timing t ...
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... Figure 13. Programmable Almost Empty Flag Timing t CLKH WCLK WEN [25] PAE RCLK REN Note 25. PAE is offset = n. Number of data words into FIFO already = n. Document Number: 38-06012 Rev. *D CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Figure 12. Half Full Timing t CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE ...
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... RCLK REN Notes 26. PAF offset = m. Number of data words written into FIFO already = 8192 for the CY7C4255V, 16384 for the CY7C4265V, 32768 for the CY7C4275V, and 65536 for the CY7C4285V. 27 the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK SKEW3 and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK ...
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... If a write is performed on this rising edge of the write clock, there are Full (m1) words of the FIFO when PAF goes LOW. 33. 8192 m words in CY7C4255V, 16384 m words in CY7C4265V, 32768m words in CY7C4275V, and 65536 m words in CY7C4285V. ...
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... Write to Last Physical Location. Document Number: 38-06012 Rev. *D Figure 18. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET Figure 19. Write Expansion Out Timing Figure 20. Read Expansion Out Timing Figure 21. Write Expansion In Timing XIS CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V PAF OFFSET PAE OFFSET Page [+] Feedback ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at t 39. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document Number: 38-06012 Rev. *D Figure 22. Read Expansion In Timing XIS [37, 38, 39] Figure 23. Retransmit Timing t PRT to update these flags. RTR CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V t RTR . RTR Page [+] Feedback ...
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... Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free) Temperature Range Commercial Industrial X = Pb-free (RoHS Compliant) Package Type STQFP Speed 3.3 V Width ×18 Depth FIFO 7C = Dual Port Company ID Cypress CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Operating Range Commercial Commercial Industrial Operating Range Commercial Operating Range Commercial Operating Range Commercial Commercial ...
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... Package Diagram Figure 24. 64-pin Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) Document Number: 38-06012 Rev. *D CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 51-85051 *B Page [+] Feedback ...
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... WEN write enable Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ms milli seconds mV milli Volts MHz Mega Hertz pF pico Farad W Watts °C degree Celcius Document Number: 38-06012 Rev. *D CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Page [+] Feedback ...
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... Document History Page Document Title: CY7C4255V/CY7C4265V/CY7C4275V/CY7C4285V 8 K/16 K/32 K/64 K × 18 Low Voltage Deep Sync FIFOs Document Number: 38-06012 Orig. of Submission REV. ECN Change ** 106473 SZV *A 122264 RBI *B 2556036 VKN/AESA *C 2896039 RAME *D 3123000 ADMU Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...