CY8C3245PVI-157 Cypress Semiconductor Corp, CY8C3245PVI-157 Datasheet

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CY8C3245PVI-157

Manufacturer Part Number
CY8C3245PVI-157
Description
CY8C3245PVI-157
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C32xxr
Datasheet

Specifications of CY8C3245PVI-157

Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
CapSense, DMA, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x12b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
General Description
With its unique array of configurable blocks, PSoC
analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I
the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051
microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives
using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog
and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
Features
Cypress Semiconductor Corporation
Document Number: 001-56955 Rev. *J
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Single cycle 8051 CPU core
Low voltage, ultra low-power
Versatile I/O system
Digital peripherals
DC to 50 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AHB
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V through 1.8-V to
5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz
Low-power modes including:
• 1-µA sleep mode with real-time clock (RTC) and
• 200-nA hibernate mode with RAM retention
28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),
two USBIOs
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46×16 segments
CapSense
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
16 to 24 programmable PLD based universal digital
blocks (UDB)
low-voltage detect (LVD) interrupt
[1]
bus access
®
[2]
support from any GPIO
)
Ordering Information
[3]
198 Champion Court
Programmable System-on-Chip (PSoC
®
3 is a true ystem level solution providing microcontroller unit (MCU), memory,
on page 106 for details.
[2]
Analog peripherals (1.71 V ≤ V
Programming, debug, and trace
Precision, programmable clocking
Temperature and packaging
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
1.024 V ±0.9-percent internal voltage reference across –40°C
to +85°C (14 ppm/°C)
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
One 8-bit, 8-Msps IDAC or 1-Msps VDAC
Two comparators with 95 ns response time
CapSense support
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Eight address and one data breakpoint
4-KB instruction trace buffer
Bootloader programming supportable through I
UART, USB, and other interfaces
3- to 24-MHz internal oscillator over full temperature and
voltage range
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 50 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
–40°C to +85°C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
transmitter receiver (UART), and I
ratio (SINAD), ±1-bit INL/DNL
San Jose
2
C). In addition to communication interfaces,
PSoC
,
CA 95134-1709
®
DDA
3: CY8C32 Family
≤ 5.5 V)
Revised March 30, 2011
2
C
Data Sheet
408-943-2600
2
C, SPI,
®
)
[2]
[+] Feedback

Related parts for CY8C3245PVI-157

CY8C3245PVI-157 Summary of contents

Page 1

... AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation Document Number: 001-56955 Rev. *J Programmable System-on-Chip (PSoC ® ...

Page 2

Contents 1. Architectural Overview ..................................................... 3 2. Pinouts ............................................................................... 5 3. Pin Descriptions .............................................................. 10 4. CPU ................................................................................... 11 4.1 8051 CPU ................................................................. 11 4.2 Addressing Modes .................................................... 11 4.3 Instruction Set .......................................................... 12 4.4 DMA and PHUB ....................................................... 16 ...

Page 3

Architectural Overview Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of ...

Page 4

In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C32 family these blocks can include four 16-bit timers, 2 counters, and PWM blocks slave, master, and ...

Page 5

This enables the device to be powered directly from a single battery or solar cell. In addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3-V supply for LCD glass drive. ...

Page 6

P2[6] (GPIO) P2[7] (GPIO, TMS, SWDIO) P1[0] (GPIO, TCK, SWDCK) P1[1] (GPIO, Configurable XRES) P1[2] (GPIO, TDO, SWV) P1[3] (GPIO, TDI) P1[4] (GPIO, nTRST) P1[5] Notes 7. The center pad on the QFN package should be connected to digital ...

Page 7

P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vssb Ind Vboost Vbat Vssd XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] ...

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P2[5] 1 (GPIO) P2[6] 2 (GPIO) P2[7] 3 (I2C0: SCL, SIO) P12[4] 4 (I2C0: SDA, SIO) P12[5] 5 (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[ Vssb Ind 11 Vboost 12 Vbat 13 Vssd ...

Page 9

Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections Vddd C6 0.1 uF Vssd 1 P2[5] 2 P2[6] 3 P2[7] 4 P12[4], SIO 5 P12[5], SIO 6 P6[4] 7 P6[5] 8 P6[6] 9 P6[7] 10 Vssb 11 Ind ...

Page 10

Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0 Low resistance output pin for high current DAC (IDAC). Extref0, Extref1 External reference input to the analog system. GPIO General purpose ...

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USBIO, D+ Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin. Pins are Do Not Use (DNU) on devices without USB. USBIO, D– Provides D– connection directly to a USB 2.0 bus. ...

Page 12

Instruction Set The 8051 instruction set is highly optimized for 8-bit handling and Boolean operations. The types of instructions supported include: Arithmetic instructions Logical instructions Data transfer instructions Boolean instructions Program branching instructions Table 4-1. Arithmetic Instructions Mnemonic ADD ...

Page 13

Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. shows ...

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Data Transfer Instructions The data transfer instructions are of three types: the core RAM, xdata RAM, and the lookup tables. The core RAM transfer includes transfer between any two core RAM locations or SFRs. These instructions can use direct, ...

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Table 4-4. Boolean Instructions Mnemonic CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit Complement direct bit ANL C, bit AND direct bit to carry ...

Page 16

Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic ACALL addr11 Absolute subroutine call LCALL ...

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DMA Features 24 DMA channels Each channel has one or more transaction descriptors (TDs) to configure channel behavior 128 total TDs can be defined TDs can be dynamically updated Eight levels of priority per channel Any digitally ...

Page 18

Scatter Gather DMA In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of ...

Page 19

CLK Arrival of new Interrupt INT_INPUT Pend bit is set on next system clock active edge PEND Interrupt is posted to ascertain the priority POST Interrupt request sent to core for processing IRQ ACTIVE_INT_NUM NA (#10) ...

Page 20

Interrupts form Fixed function blocks, DMA and UDBs Interrupts from UDBs Interrupts from Fixed Function Blocks Interrupt Interrupts 0 to routing logic 30 from DMA to select 31 sources Document Number: 001-56955 Rev. *J ...

Page 21

Table 4-8. Interrupt Vector Table # Fixed Function DMA 0 LVD phub_termout0[0] 1 ECC phub_termout0[1] 2 Reserved phub_termout0[2] 3 Sleep (Pwr Mgr) phub_termout0[3] 4 PICU[0] phub_termout0[4] 5 PICU[1] phub_termout0[5] 6 PICU[2] phub_termout0[6] 7 PICU[3] phub_termout0[7] 8 PICU[4] phub_termout0[8] 9 PICU[5] ...

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Memory 5.1 Static RAM CY8C32 Static RAM (SRAM) is used for temporary data storage SRAM is provided and can be accessed by the 8051 or the DMA controller. See Memory Map Simultaneous access of ...

Page 23

Nonvolatile Latches (NVLs) PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table 5-2. Table 5-2. Device Configuration NVL Register Map Register Address ...

Page 24

External Memory Interface CY8C32 provides an external memory interface (EMIF) for connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to ...

Page 25

Figure 5-2. 8051 Internal Data Space 0x00 4 Banks, R0-R7 Each 0x1F 0x20 Bit-Addressable Area 0x2F 0x30 Lower Core RAM Shared with Stack Space (direct and indirect addressing) 0x7F 0x80 Upper Core RAM Shared Special Function Registers with Stack Space ...

Page 26

I/O Port SFRs The I/O ports provide digital input sensing, output drive, pin interrupts, connectivity for analog inputs and outputs, LCD, and access to peripherals through the DSI. Full information on I/O ports is found in I/O System and Routing ...

Page 27

Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin IMO 3 MHz ±1% over voltage and temperature MHzECO 4 MHz Crystal dependent DSI 0 MHz Input dependent PLL 24 MHz Input dependent Doubler 12 MHz Input dependent ILO 1 kHz ...

Page 28

The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range MHz. Its input and feedback dividers supply 4032 discrete ratios to ...

Page 29

This is only possible if there are multiple precision clock sources. 6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks ...

Page 30

Vddio2 0.1µ Supply Digital Domain Vssd I/O Supply 0.1µF Vddio1 Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6. ...

Page 31

Power Modes PSoC 3 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing ...

Page 32

Figure 6-5. Power Mode Transitions Active Manual Sleep Buzz Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or ...

Page 33

The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz kHz to optimize efficiency and component cost. The 100 kHz, 400 kHz, and 2 MHz switching frequencies are generated using oscillators internal to the boost ...

Page 34

At these times the PRES circuit is also buzzed to allow periodic voltage monitoring. ALVI, DLVI, AHVI – Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when V ...

Page 35

Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable ...

Page 36

Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...

Page 37

Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. drive modes. Table 6-6 shows the I/O pin’s drive ...

Page 38

High Impedance Analog The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O’s digital input buffer due to a floating voltage. This state is recommended for ...

Page 39

Analog Connections These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the V supply voltage to which DDIO the GPIO ...

Page 40

Over Voltage Tolerance All I/O pins provide an over voltage tolerance feature at any operating There are no current limitations for the SIO pins as they present a high impedance load to the external circuit where ...

Page 41

Figure 7-1. CY8C32 Digital Programmable Architecture Digital Core System and Fixed Function Peripherals DSI Routing Interface UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB ...

Page 42

Document Number: 001-56955 Rev. *J Figure 7-2. PSoC Creator Framework ® PSoC 3: CY8C32 Family Data Sheet Page 42 of 119 [+] Feedback ...

Page 43

Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...

Page 44

PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...

Page 45

Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators ...

Page 46

Independent of the ALU operation, these functions are available: Shift left Shift right Nibble swap Bitwise OR mask 7.2.2.3 Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers ...

Page 47

Clock Generation Each subcomponent block of a UDB including the two PLDs, the datapath, and Status and Control, has a clock selection and control block. This promotes a fine granularity with respect to allocating clocking resources to UDB component ...

Page 48

Figure 7-13. Digital System Interconnect Tim ers Interrupt I2C C ounters C ontroller C ontroller D igital System R outing I igital System R outing I/F G lobal ...

Page 49

USB PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO pins, which are ...

Page 50

I C provides hardware address detect of a 7-bit address without CPU intervention. Additionally the device can wake from low-power modes on a 7-bit hardware address match. If wakeup 2 functionality is required pin connections are limited ...

Page 51

Analog Subsystem The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to each other and also to any pin on the device, providing a high level ...

Page 52

Analog Routing The CY8C32 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this ...

Page 53

ExVrefL ExVrefL1 GPIO P0[4] GPIO P0[5] GPIO * i0 P0[6] GPIO * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] P4[2] vref_cmp1 cmp1_vref (0.256V) GPIO bg_vda_res_en Vdda Vdda/2 P4[3] refbuf_vref1 (1.024V) GPIO refbuf_vref2 (1.2V) P4[4] refsel[1:0] GPIO ...

Page 54

Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C32, four in the left half (abusl [0:3]) and four in the ...

Page 55

Single Sample In Single Sample mode, the ADC performs one sample conversion on a trigger. In this mode, the ADC stays in standby state waiting for the SoC signal to be asserted. When SoC is signaled the ADC performs ...

Page 56

From Analog Routing 8.3.2 LUT The CY8C32 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of ...

Page 57

LCD Direct Drive The PSoC Liquid Crystal Display (LCD) driver system is a highly configurable peripheral designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need for ...

Page 58

DAC The CY8C32 parts contain a Digital to Analog Converter (DAC). The DAC is 8-bit and can be configured for either voltage or current output. The DAC supports CapSense, power supply regulation, and waveform generation. The DAC has the ...

Page 59

Programming, Debug Interfaces, Resources PSoC devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. Three interfaces are available: JTAG, SWD, and SWV. JTAG and SWD support all programming and debug features of the device. ...

Page 60

Single Wire Viewer Interface The SWV interface is closely associated with SWD but can also be used independently. SWV data is output on the JTAG interface’s TDO pin. If using SWV, you must configure the device for SWD, not ...

Page 61

Development Support The CY8C32 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. 10.1 Documentation A suite of documentation, supports the CY8C32 family ...

Page 62

Electrical Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, ...

Page 63

Device Level Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog ...

Page 64

Table 11-2. DC Specifications (continued) Parameter Description [20] Sleep Mode CPU = OFF RTC = ON (= ECO32K ON, in low-power mode) Sleep timer = ON (= ILO ON at [21] 1 kHz) WDT = OFF Wake ...

Page 65

Figure 11-1. Active Mode Current vs F Temperature = 25 °C Figure 11-3. Active Mode Current MHz CPU Document Number: 001-56955 Rev 3.3 V, Figure 11-2. Active Mode Current vs Temperature ...

Page 66

Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency BUSCLK Svdd V ramp rate DD T Time from IO_INIT DDD DDA ≥ IPOR to I/O ports set to their reset states T ...

Page 67

Power Regulators Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage ...

Page 68

Inductive Boost Regulator. Table 11-6. Inductive Boost Regulator DC Specifications Unless otherwise specified, operating conditions are µF || 0.1 µF BOOST Parameter Description V Input voltage BAT Includes startup [23, 24] I Load current OUT ...

Page 69

Table 11-7. Inductive Boost Regulator AC Specifications Unless otherwise specified, operating conditions are µF || 0.1 µF. BOOST Parameter Description V Ripple voltage (peak-to-peak) RIPPLE F Switching frequency SW Table 11-8. Recommended External Components for Boost ...

Page 70

Figure 11-8. Efficiency vs V OUT mA, V ranges from 0 OUT BAT Figure 11-10. Efficiency vs I OUT 3.3 V BAT OUT Figure 11-12. Efficiency vs Switching ...

Page 71

Inputs and Outputs Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.1.1 GPIO Table 11-9. GPIO DC Specifications Parameter Description ...

Page 72

Table 11-10. GPIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode TfallF Fall time in Fast Strong Mode TriseS Rise time in Slow Strong Mode TfallS Fall time in Slow Strong Mode GPIO output operating frequency 2.7 ...

Page 73

SIO Table 11-11. SIO DC Specifications Parameter Description Vinmax Maximum input voltage Vinref Input voltage reference (Differ- ential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold V GPIO mode IH [30] Differential input mode ...

Page 74

Figure 11-17. SIO Output HighVoltage and Current, Unregulated Mode Figure 11-19. SIO Output High Voltage and Current, Regulated Mode Table 11-12. SIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode [32] (90/10%) TfallF Fall time in Fast ...

Page 75

Table 11-12. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 2.7 V < V < 5.5 V, Unregu- DDIO lated output (GPIO) mode, fast strong drive mode 1.71 V < V < 2.7 V, Unregu- DDIO lated output ...

Page 76

USBIO For operation in GPIO mode, the standard range for V Table 11-13. USBIO DC Specifications Parameter Description Rusbi USB D+ pull-up resistance Rusba USB D+ pull-up resistance Vohusb Static output high Volusb Static output low Vohgpio Output voltage ...

Page 77

Table 11-14. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...

Page 78

XRES Table 11-16. XRES DC Specifications Parameter Description V Input voltage high threshold IH V Input voltage low threshold IL Rpullup Pull-up resistor [33] C Input capacitance IN V Input voltage hysteresis H [33] (Schmitt-Trigger) Idiode Current through protection ...

Page 79

Analog Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.2.1 Delta-sigma ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode fclk = 6.144 MHz Reference = ...

Page 80

Table 11-19. Delta-sigma ADC AC Specifications Parameter Description Startup time [36] THD Total harmonic distortion 12-Bit Resolution Mode SR12 Sample rate, continuous, high power BW12 Input bandwidth at max sample rate SINAD12int Signal to noise ratio, 12-bit, internal [36] reference ...

Page 81

Voltage Reference Table 11-21. Voltage Reference Specifications See also ADC external reference specifications in Section Parameter Description V Precision reference voltage REF 11.2.3 Analog Globals Table 11-22. Analog Globals Specifications Parameter Description Rppag Resistance pin-to-pin through analog global Rppmuxbus ...

Page 82

Current Digital-to-analog Converter (IDAC) See the IDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-25. IDAC DC Specifications Parameter Description Resolution I Output current ...

Page 83

Table 11-25. IDAC DC Specifications (continued) Parameter Description I Operating current, code = 0 DD Figure 11-26. IDAC INL vs Input Code, Range = 255 µA, Source Mode Document Number: 001-56955 Rev. *J PSoC Conditions Min Slow mode, source mode, ...

Page 84

Figure 11-28. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-30. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Document Number: 001-56955 Rev. *J ® PSoC 3: CY8C32 Family Figure 11-29. IDAC DNL vs ...

Page 85

Figure 11-32. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Figure 11-34. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Document Number: 001-56955 Rev. *J ® PSoC 3: CY8C32 Family ...

Page 86

Table 11-26. IDAC AC Specifications Parameter Description F Update rate DAC T Settling time to 0.5 LSB SETTLE Figure 11-36. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V Figure 11-38. ...

Page 87

Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-27. VDAC DC Specifications Parameter Description Resolution INL1 ...

Page 88

Figure 11-41. VDAC INL vs Temperature Mode Figure 11-43. VDAC Full Scale Error vs Temperature Mode Figure 11-45. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode Document Number: 001-56955 Rev. *J ® PSoC 3: CY8C32 ...

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Table 11-28. VDAC AC Specifications t Parameter Description F Update rate DAC TsettleP Settling time to 0.1%, step 25% to 75% TsettleN Settling time to 0.1%, step 75% to 25% Figure 11-47. VDAC Step Response, Codes 0x40 - 0xC0, 1 ...

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Temperature Sensor Table 11-29. Temperature Sensor Specifications Parameter Description Temp sensor accuracy 11.2.8 LCD Direct Drive Table 11-30. LCD Direct Drive DC Specifications Parameter Description I LCD system operating current CC I Current per segment driver CC_SEG V LCD ...

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Digital Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.3.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; ...

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Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator.. Table 11-36. PWM DC Specifications Parameter ...

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USB Table 11-42. USB DC Specifications Parameter Description V Device supply for USB operation USB_5 V USB_3.3 V USB_3 I Device supply current in device active USB_Configured mode, bus clock and IMO = 24 MHz I Device supply current ...

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Memory Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.4.1 Flash Table 11-44. Flash DC Specifications Parameter Description Erase and program voltage Table 11-45. Flash AC Specifications Parameter Description T ...

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Table 11-47. EEPROM AC Specifications Parameter Description T Single row erase/write cycle time WRITE EEPROM data retention time, retention period measured from last erase cycle 11.4.3 Nonvolatile Latches (NVL)) Table 11-48. NVL DC Specifications Parameter Description Erase and program voltage ...

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External Memory Interface Figure 11-51. Asynchronous Read Cycle Timing EM_ CEn Taddrv EM_ Addr EM_ OEn EM_ WEn EM_ Data Table 11-52. Asynchronous Read Cycle Specifications Parameter Description [42] T EMIF clock period Tcel EM_CEn low time Taddrv EM_CEn ...

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Figure 11-52. Asynchronous Write Cycle Timing Taddrv EM_ Addr EM_ CEn EM_ WEn EM_ OEn Tdcev EM_ Data Table 11-53. Asynchronous Write Cycle Specifications Parameter Description [43] T EMIF clock period Tcel EM_CEn low time Taddrv EM_CEn low to EM_Addr ...

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EM_ Clock EM_ CEn EM_ Addr EM_ OEn EM_ Data EM_ ADSCn Table 11-54. Synchronous Read Cycle Specifications Parameter Description [44] T EMIF clock period Tcp/2 EM_Clock pulse high Tceld EM_CEn low to EM_Clock high Tcehd EM_Clock high to EM_CEn ...

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EM_ Clock EM_ CEn EM_ Addr EM_ WEn EM_ Data EM_ ADSCn Table 11-55. Synchronous Write Cycle Specifications Parameter Description [45] T EMIF clock Period Tcp/2 EM_Clock pulse high Tceld EM_CEn low to EM_Clock high Tcehd EM_Clock high to EM_CEn ...

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PSoC System Resources Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.5.1 POR with Brown Out For brown out detect in regulated mode, V mode. Table 11-56. Precise Power-on Reset ...

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Interrupt Controller Table 11-60. Interrupt Controller AC Specifications Parameter Description Delay from interrupt signal input to ISR code execution from ISR code 11.5.4 JTAG Interface TCK T_TDI_setup TDI TDO T_TMS_setup TMS Table 11-61. JTAG Interface AC Specifications Parameter Description ...

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SWD Interface SWDCK SWDIO (PSoC 3 reading on SWDIO) SWDIO (PSoC 3 writing to SWDIO) Table 11-62. SWD Interface AC Specifications Parameter Description f_SWDCK SWDCLK frequency T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T_SWDI_hold SWDIO ...

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Internal Main Oscillator Table 11-66. IMO DC Specifications Parameter Description Supply current 24 MHz – USB mode 24 MHz – non USB mode 12 MHz 6 MHz 3 MHz Figure 11-57. IMO Current vs. Frequency Table 11-67. IMO AC ...

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Figure 11-58. IMO Frequency Variation vs. Temperature 11.6.3 Internal Low-Speed Oscillator Table 11-68. ILO DC Specifications Parameter Description Operating current I CC Leakage current Table 11-69. ILO AC Specifications Parameter Description Startup time, all frequencies ILO frequencies (trimmed) 100 kHz ...

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External Crystal Oscillator Table 11-70. ECO AC Specifications Parameter Description F Crystal frequency range 11.6.5 External Clock Reference Table 11-71. External Clock Reference AC Specifications Parameter Description External frequency range Input duty cycle range Input edge rate 11.6.6 Phase–Locked ...

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... Del-Sig CY8C3245AXI-166 – 12-bit Del-Sig CY8C3245LTI-124 – 12-bit Del-Sig CY8C3245LTI-144 – 12-bit Del-Sig CY8C3245PVI-167 – 12-bit Del-Sig ✔ CY8C3245AXI-148 12-bit Del-Sig ✔ CY8C3245LTI-142 12-bit Del-Sig Notes 54. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs ...

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... Table 12-1. CY8C32 Family with Single Cycle 8051 (continued) MCU Core Part Number ✔ CY8C3245LTI-164 12-bit Del-Sig ✔ CY8C3245PVI-157 12-bit Del-Sig ✔ CY8C3245AXI-154 12-bit Del-Sig CY8C3245LTI-129 ✔ 12-bit Del-Sig CY8C3245LTI-160 ✔ 12-bit Del-Sig CY8C3245PVI-150 ✔ 12-bit Del-Sig 64 KB Flash CY8C3246AXI-137 50 64 ...

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Part Numbering Conventions PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric ( … …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC ...

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Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A T Operating junction temperature J Package θJA (48-pin SSOP) Tja Package θJA (48-pin QFN) Tja Package θJA (68-pin QFN) Tja Package θJA (100-pin TQFP) Tja Package θJC ...

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Figure 13-1. 48-pin (300 mil) SSOP Package Outline 24 25 0.620 0.630 0.088 0.092 0.025 BSC TOP VIEW 7.00±0. PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE ...

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Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version) TOP VIEW 8.000±0.100 PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE ...

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Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...

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Table 14-1. Acronyms Used in this Document (continued) Acronym Description PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration datasheet ...

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Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples ...

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Revision History ® Description Title: PSoC 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-56955 Submission Orig. of Rev. ECN No. Date Change ** 2796903 11/04/09 *A 2824546 12/09/09 *B 2873322 02/04/10 Document Number: 001-56955 Rev. *J ...

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Description Title: PSoC 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-56955 *C 2903576 04/01/10 Document Number: 001-56955 Rev. *J MKEA Updated Vb pin in PCB Schematic. Updated Tstartup parameter in AC Specifications table. Added Load regulation ...

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Description Title: PSoC 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-56955 *D 2938381 05/27/10 *E 2958674 06/22/10 *F 2989685 08/04/10 *G 3078568 11/04/10 *H 3107314 12/10/2010 *I 3179219 02/22/2011 Document Number: 001-56955 Rev. *J MKEA Replaced ...

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Description Title: PSoC 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-56955 *J 3200146 03/28/2011 Document Number: 001-56955 Rev. *J MKEA Removed Preliminary status from the data sheet. Updated JTAG ID Deleted Cin_G1, ADC input capacitance from ...

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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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