CYV15G0204TRB-BGXC Cypress Semiconductor Corp, CYV15G0204TRB-BGXC Datasheet
CYV15G0204TRB-BGXC
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CYV15G0204TRB-BGXC Summary of contents
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... CYV15G0204TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. Each transmit (TX) channel of the CYV15G0204TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from ...
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... Each receive (RX) channel of the CYV15G0204TRB HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs ...
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... Clock Multiplier Character-Rate Clock A TXBISTA PABRSTA Bit-Rate Clock B Transmit PLL Transmit PLL OEB[2..1] Clock Multiplier B Clock Multiplier Character-Rate Clock B TXBISTB PABRSTB CYV15G0204TRB = Internal Signal RESET OEA[2..1] OUTA1+ OUTA1– OUTA2+ OUTA2– OEB[2..1] OUTB1+ OUTB1– OUTB2+ OUTB2– Page [+] Feedback ...
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... RXRATEC Recovered Serial Data Reclocker ROE[2..1]C Output PLL Clock Multiplier RXBISTD[1:0] RXRATED Recovered Serial Data Reclocker ROE[2..1]D Output PLL Clock Multiplier D CYV15G0204TRB = Internal Signal RESET TRST JTAG TMS TCLK Scan TDI TDO LFIC 10 RXDC[9:0] BISTSTC 2 RXCLKC+ RXCLKC– ...
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... Device Configuration and Control Block Diagram WREN Device Configuration ADDR[3:0] and Control Interface DATA[6:0] Document Number : 38-02101 Rev. *D CYV15G0204TRB = Internal Signal TXRATE[A..B] TXCKSEL[A..B] PABRST[A..B] TOE[2..1][A..B] TXBIST[A..B] RXRATE[C..D] SDASEL[2..1][C..D][1:0] TRGRATE[C..D] RXPLLPD[C..D] RXBIST[C..D][1:0] ROE[2..1][C..D] Page [+] Feedback ...
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... CLKD– DA[1] RX BIST ADDR TRG TX GND GND DD[1] STD [2] CLKD+ CLKOA RX ADDR ADDR TX GND NC GND DD[0] [3] [1] ERRA GND NC NC GND DD[2] CLKOD CLKA CYV15G0204TRB TOUT TOUT TOUT GND A2– B1– B2– TOUT TOUT TOUT A2+ B1+ B2+ SPD LDTD TRST TDO ...
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... CLKD– [0] DA[ TRG ADDR BIST GND GND DA[3] CLKOA CLKD+ [2] STD TX TX ADDR ADDR GND NC GND DA[2] ERRA [1] [ GND NC NC GND DA[0] CLKA CLKOD CYV15G0204TRB ROUT IN ROUT IN ROUT D1– D1– C2– C2– C1– C1– ROUT IN ROUT IN ROUT D1+ D1+ C2+ C2+ C1+ C1+ ...
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... Pin Definitions CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDA[7:0] LVTTL Input, TXDB[7:0] synchronous, sampled by the associated TXCLKx or [2] REFCLKx TXERRA LVTTL Output, TXERRB synchronous to [3] REFCLKx ...
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... Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description Receive Path Data and Status Signals RXDC[9:0] LVTTL Output, RXDD[9:0] synchronous to the RXCLK± output BISTSTC LVTTL Output, BISTSTD synchronous to the RXCLKx ± output REPDOC ...
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... Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description LDTDEN LVTTL Input, internal pull-up ULCC LVTTL Input, ULCD internal pull-up [4] SPDSELA 3-Level Select SPDSELB static control input SPDSELC SPDSELD INSELC LVTTL Input, INSELD asynchronous ...
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... Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description DATA[6:0] LVTTL input asynchronous, internal pull-up Internal Device Configuration Latches [6] RXRATE[C..D] Internal Latch [6] SDASEL[2..1][C..D] Internal Latch [1:0] [6] TXCKSEL[A..B] Internal Latch [6] TXRATE[A..B] Internal Latch [6] TRGRATE[C..D] ...
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... It also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as TXCLKOx. Each clock multiplier PLL can accept a REFCLKx± input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0204TRB clock CYV15G0204TRB Page [+] Feedback ...
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... CYV15G0204TRB Receive Data Path Serial Line Receivers Signaling Rate (Mbps) Two differential Line Receivers, INx1± and INx2±, are available on each channel for accepting serial data streams. 195– ...
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... Document Number : 38-02101 Rev. *D [7] Receive Channel Enabled The CYV15G0204TRB contains two receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface. When the RXPLLPDx latch = 0, the associated PLL and analog circuitry of the channel is disabled ...
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... Device Reset State When the CYV15G0204TRB is reset by assertion of RESET, all state machines, counters, and configuration latches in the device are initialized to a reset state. Additionally, the JTAG controller must also be reset for valid operation (even if JTAG testing is not performed). See “ ...
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... PABRSTx is a self clearing latch. This eliminates the requirement of writing complete the initialization of the Phase Alignment Buffer. Document Number : 38-02101 Rev. *D CYV15G0204TRB The first and second rows of each channel (address numbers and 10) are the static control latches. The third row of latches for each channel (address numbers and 11) are the dynamic control latches that are associated with enabling dynamic functions within the device ...
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... If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Document Number : 38-02101 Rev. *D CYV15G0204TRB Page [+] Feedback ...
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... DATA3 TXBISTA TXBISTB SDASEL1C[1] SDASEL1C[0] RXBISTC[ SDASEL1D[1] SDASEL1D[0] RXBISTD[0] X INTERNAL TEST REGISTERS DO NOT WRITE TO THESE ADDRESSES CYV15G0204TRB Reset DATA2 DATA1 DATA0 Value 1011111 0 TXCKSELA TXRATEA 1010110 OE2A OE1A PABRSTA 1011001 1011111 0 TXCKSELB TXRATEB 1010110 OE2B OE1B PABRSTB 1011001 0 0 RXRATEC 1011111 X ...
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... JTAG Support The CYV15G0204TRB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs, the REFCLKx± clock inputs, and the TRGCLKx± clock inputs. The high-speed serial inputs and outputs are not part of the JTAG test chain ...
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... Monitor Data Received {BISTSTx, RXDx[0], RXDx[1]} = BIST_START (101) Start of BIST Detected Compare Next Character Match End-of-BIST State Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_LAST_GOOD (010) BIST_ERROR (110) CYV15G0204TRB Receive BIST Detected LOW RX PLL Out of Lock {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) No Page [+] Feedback ...
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... Document Number : 38-02101 Rev. *D Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0204TRB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range + 0.5V CC ...
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... CYV15G0204TRB DC Electrical Characteristics Parameter Description Differential CML Serial Outputs: TOUTA1, TOUTA2, TOUTB1, TOUTB2ROUTC1, ROUTC2, ROUTD1, ROUTD2 V Output HIGH Voltage OHC (V Referenced Output LOW Voltage OLC (V Referenced Output Differential Voltage ODIF |(OUT+) (OUT)| Differential Serial Line Receiver Inputs: INC1 ...
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... CYV15G0204TRB AC Electrical Characteristics Parameter CYV15G0204TRB Transmitter LVTTL Switching Characteristics Over the Operating Range f TXCLKx Clock Cycle Frequency TS t TXCLKx Period=1/f TXCLK TS [16] t TXCLKx HIGH Time TXCLKH [16] t TXCLKx LOW Time TXCLKL [16, 17, 18, 19] t TXCLKx Rise Time TXCLKR [16, 17, 18, 19] t TXCLKx Fall Time TXCLKF Transmit Data Set-up Time to ...
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... JTAG Test Clock Period TCLK CYV15G0204TRB Device RESET Characteristics Over the Operating Range t Device RESET Pulse Width RST CYV15G0204TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range Parameter t Bit Time B [16] t CML Output Rise Time 2080% (CML Test Load) ...
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... Reclocker Jitter Generation - SD Data Rate JRGENSD [16, 25] t Reclocker Jitter Generation - HD Data Rate JRGENHD CYV15G0204TRB Receive PLL Characteristics Over the Operating Range t Receive PLL lock to input data stream (cold start) RXLOCK Receive PLL lock to input data stream t Receive PLL Unlock Rate RXUNLOCK ...
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... CYV15G0204TRB HOTLink II Transmitter Switching Waveforms Transmit Interface Write Timing REFCLKx selected TXRATEx = 1 REFCLKx TXDx[9:0] Transmit Interface TXCLKOx Timing TXRATEx = 1 REFCLKx Note 28 TXCLKOx (internal) Transmit Interface TXCLKOx Timing t REFH TXRATEx = 0 REFCLKx Note28 TXCLKOx Notes 26. When REFCLKx± is configured for half-rate operation (TXRATEx = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using both the rising and falling edges of REFCLKx. 27. The TXCLKOx output remains at the character rate regardless of the state of TXRATEx and does not follow the duty cycle of REFCLKx± ...
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... Switching Waveforms for the CYV15G0204TRB HOTLink II Receiver Receive Interface Read Timing RXRATEx = 0 RXCLKx+ RXCLKx– RXDx[9:0] Receive Interface Read Timing RXRATEx = 1 RXCLKx+ RXCLKx– RXDx[9:0] Bus Configuration Write Timing ADDR[3:0] DATA[6:0] WREN Document Number : 38-02101 Rev RXCLKP t RXDV– t RXDV+ t RXCLKP t RXDV– ...
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... POWER E03 VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER E19 VCC POWER E20 VCC POWER CYV15G0204TRB Ball Signal Name Signal Type ID F17 NC NO CONNECT F18 NC NO CONNECT F19 TXCLKOB LVTTL OUT F20 NC NO CONNECT G01 GND GROUND ...
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... LVTTL IN V16 VCC POWER V17 NC NO CONNECT V18 NC NO CONNECT V19 NC NO CONNECT V20 NC NO CONNECT W01 VCC POWER CYV15G0204TRB Ball Signal Name Signal Type ID L19 NC NO CONNECT L20 TXDB[6] LVTTL IN M01 RXDC[6] LVTTL OUT M02 RXDC[7] LVTTL OUT W03 LFID ...
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... POWER Ordering Information Speed Ordering Code Standard CYV15G0204TRB-BGXC Package Diagram Figure 3. 256-Lead L2 Ball Grid Array ( 1.57 mm) BL256 HOTLink is a registered trademark and HOTLink trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document Number : 38-02101 Rev. *D ...
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... Document History Page Document Title: CYV15G0204TRB Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer Document Number: 38-02101 ISSUE REV. ECN NO. DATE ** 244348 See ECN *A 338721 See ECN *B 384307 See ECN *C 1034060 See ECN *D 2897032 03/19/10 Document Number : 38-02101 Rev. *D © ...