CYWUSB6935-48LFXI Cypress Semiconductor Corp, CYWUSB6935-48LFXI Datasheet - Page 18

• Manufacturer Part Number: CYWUSB6935-48LFXI
• Description: IC,Upconverter And Downconverter,LLCC,48PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-48LFXI

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1626

Table 23. Wake Status
Table 24. Analog Control
Table 25. Channel
Document #: 38-16008 Rev. *E
Bit
6:0 Channel
4:3 Reserved
7:1 Reserved
Bit
Bit
7 Reserved This bit is reserved and should be written with zero.
7
6
5
2
1
0
0
Reserved
Reserved
Reserved
Reg Write
Control
MID Read
Enable
PA Output
Enable
PA Invert
Reset
Wakeup Status Wakeup status.
7
7
7
Name
Addr: 0x1D
Addr: 0x20
Addr: 0x21
Name
Name
The Channel register (Reg 0x21) is used to determine the Synthesizer frequency. A value of 2 corresponds to a
communication frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The channels
are separated from each other by 1 MHz intervals.
Limit application usage to channels 2–79 to adhere to FCC regulations. FCC regulations require that channels 0
and 1 and any channel greater than 79 be avoided. Use of other channels may be restricted by other regulatory
agencies. The application MCU must ensure that this register is modified before transmitting data over the air for
the first time.
Reg Write
Control
These bits are reserved. This register is read-only.
0 = Wake interrupt not pending
1 = Wake interrupt pending
This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register
(Reg 0x1D). This register is read-only.
6
6
6
This bit is reserved and should be written with zero.
Enables write access to Reg 0x2E and Reg 0x2F.
1 = Enables write access to Reg 0x2E and Reg 0x2F
0 = Reg 0x2E and Reg 0x2F are read-only
The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when
reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
1 = Enables read of MID registers
0 = Disables read of MID registers
These bits are reserved and should be written with zeroes.
The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power
amplifier.
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set
high. PA Output Enable and PA Invert cannot be simultaneously changed.
1 = PACTL active low
0 = PACTL active high
The Reset bit is used to generate a self-clearing device reset.
1 = Device Reset. All registers are restored to their default values.
0 = No Device Reset.
MID Read
Enable
5
5
5
Reserved
Reserved
REG_ANALOG_CTL
REG_WAKE_STAT
4
4
4
REG_CHANNEL
Description
Reserved
Channel
Description
Description
3
3
3
PA Output
Enable
2
2
2
PA Invert
1
1
1
CYWUSB6935
Default: 0x01
Default: 0x00
Default: 0x00
Wakeup Status
Page 18 of 34
Reset
0
0
0
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