CYWUSB6935-48LTXC Cypress Semiconductor Corp, CYWUSB6935-48LTXC Datasheet - Page 10

• Manufacturer Part Number: CYWUSB6935-48LTXC
• Description: CYWUSB6935-48LTXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-48LTXC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Table 7. Configuration
Table 8. SERDES Control
Document #: 38-16008 Rev. *E
7:2 Reserved
1:0 IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.
Bit
7:4 Reserved
2:0 EOF Length
Bit
3
SERDES
Enable
7
7
Name
Addr: 0x05
Addr: 0x06
Name
These bits are reserved and should be written with zeroes.
11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z)
10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z)
01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0)
00 = CMOS Inverted (IRQ asserted = 0, IRQ deasserted = 1)
These bits are reserved and should be written with zeroes.
The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.
1 = SERDES enabled
0 = SERDES disabled, bit-serial mode enabled
When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the
use of the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through
the use of the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid
the need to manage the timing required by the bit-serial mode.
The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without
valid data before an EOF event will be generated. When in receive mode and a valid bit has been received
the EOF event can then be identified by the number of bit times that expire without correlating any new data.
The EOF event causes data to be moved to the proper SERDES Data Register and can also be used to
generate interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid
reception.
6
6
Reserved
5
5
Reserved
REG_SERDES_CTL
4
4
REG_CONFIG
SERDES
Description
Enable
Description
3
3
2
2
EOF Length
1
1
CYWUSB6935
IRQ Pin Select
Default: 0x01
Default: 0x03
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