DAC10GSZ Analog Devices Inc, DAC10GSZ Datasheet - Page 8

• Manufacturer Part Number: DAC10GSZ
• Description: SOL-18 MARKED AS "DAC10G"
• Manufacturer: Analog Devices Inc

Specifications of DAC10GSZ

• Settling Time: 85ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 285mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DAC10
APPLICATIONS
Reference Amplifier Setup
The DAC10 is a multiplying D/A converter in which the output
current is the product of a digital number and the input refer-
ence current. The reference current may be fixed or may vary
from nearly zero to 2 mA. The full-scale output current is a
linear function of the reference current and is given by:
where I
In positive reference applications, an external positive reference
voltage forces current through R16 into the V
(Pin 16) of the reference amplifier. Alternatively, a negative
reference may be applied to V
flows from ground through R16 into V(+) as in the positive
reference case. This negative reference connection has the ad-
vantage of a very high impedance presented at Pin 17. R17
(nominally equal to R16) is used to cancel bias current errors;
R17 may be eliminated with only a minor increase in error.
Bipolar references may be accommodated by offsetting V
Pin 17. The negative common-mode range of the reference
amplifier is given by: V
The positive common-mode range is V+ less 1.8 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5 V TTL logic supply is not recommended as
a reference. If a regulated power supply is used as a reference,
R16 should be split into two resistors with the junction bypassed
to ground with a 0.1 F capacitor.
For most applications, the tight relationship between I
I
scale trimming may be accomplished by adjusting the value of
R16, or by using a potentiometer for R16. An improved method
of full-scale trimming that eliminates potentiometer TC effect is
shown in the Recommended Full-Scale Adjustment circuit.
The reference amplifier must be compensated by using a capaci-
tor from Pin 18 to V–. For fixed reference operation, a 0.01 F
capacitor is recommended. For variable reference applications,
see section entitled Reference Amplifier Compensation for Mul-
tiplying Applications.
FS
will eliminate the need for trimming I
REF
TYPICAL VALUES:
R
+V
R
0V
IN
EQ
IN
Figure 18. Pulsed Reference Operation
= 1k
equals current flowing into Pin 16.
= 2V
=
R
1
IN
R
+
IN
R
1
1
P
+
+V
I
R
R
REF
FR
P
REF
R
1
CM
R
EQ
REF
– = V– plus (I
= 800
1023
1024
OPTIONAL RESISTOR
FOR OFFSET INPUTS
16
17
REF
(–) at Pin 17; reference current
2 I
DAC10
NO CAP
REF
REF
REF
. If required, full-
2 k ) plus 2 V.
REF
4
2
(+) terminal
R
R
L
L
REF
REF
and
or
–8–
Multiplying Operation
The DAC10 provides excellent multiplying performance with an
extremely linear relationship between I
of 4 mA to 4 A. Monotonic operation is maintained over a
typical range of I
Reference Amplifier Compensation for Multiplying Applications
AC reference applications will require the reference amplifier to
be compensated using a capacitor from Pin 18 to V–. The value
of this capacitor depends on the impedance presented to Pin 16
for R16 values of 1.0 k , 2.5 k and 5.0 k , minimum values
of C
proportionately increased values of C
For fastest response to a pulse, low values of R16 enabling small
C
ance such as a transistor current source, none of the above val-
ues will suffice and the amplifier must be heavily compensated,
which will decrease overall bandwidth and slew rate. For R16 =
1 k and C
enabling a transition from I
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (I
occurs in 120 ns when the equivalent impedance at Pin 16 is
200
LOGIC INPUTS
The DAC10 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made pos-
sible by the large input swing capability, 2 A logic input current
and completely adjustable logic threshold voltage. For V– = –15 V,
the logic inputs may swing between –5 and +18 V. This enables
direct interface with +15 V CMOS logic, even when the DAC10
is powered from a +5 V supply. Minimum input logic swing and
minimum logic threshold voltage are given by: V– plus (l
2 k ) plus 3 V. The logic threshold may be adjusted over a wide
range by placing an appropriate voltage at the logic threshold
control Pin (Pin 1, V
relationship between V
with V
ground Pin 1. When interfacing ECL, an I
mended. For interfacing other logic families, see Figure 17. For
general setup of the logic control circuit, it should be noted that
Pin 1 will sink 1.1 mA typical; external circuitry should be de-
signed to accommodate this current.
Fastest settling times are obtained when Pin 1 sees a low imped-
ance. If Pin 1 is connected to a 1 k divider, for example, it
should be bypassed to ground by a 0.01 F capacitor.
s, which is relatively independent of R
C
values should be used. If Pin 16 is driven by a high imped-
C
are 15 pF, 37 pF and 75 pF. Larger values of R16 require
TH
and C
REF
nominally 1.4 V above V
C
= 0) condition. Full-scale transition (0 mA to 2 mA)
C
= 15 pF, the reference amplifier slews at 4 mA/ s
= 0. This yields a reference slew rate of 16 mA/
REF
from 100 A to 2 mA.
LC
LC
). The appropriate graph shows the
and V
REF
= 0 to I
TH
LC
over the temperature range,
. For TTL interface, simply
C
FS
REF
for proper phase margin.
IN
and I
and V
= 2 mA in 500 ns.
REF
= 1 mA is recom-
REF
IN
values.
over a range
REV. D
REF