DSPIC33EP256MU810-I/PF Microchip Technology, DSPIC33EP256MU810-I/PF Datasheet
DSPIC33EP256MU810-I/PF
Specifications of DSPIC33EP256MU810-I/PF
Available stocks
Related parts for DSPIC33EP256MU810-I/PF
DSPIC33EP256MU810-I/PF Summary of contents
Page 1
... PIC24EPXXXGU810/814 2009-2011 Microchip Technology Inc. Data Sheet High-Performance, 16-bit Digital Signal Controllers and Microcontrollers Preliminary DS70616E ...
Page 2
... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009-2011, Microchip Technology Incorporated, Printed in the U ...
Page 3
... Single-Cycle shifts for up to 40-bit Data • 16x16 Fractional Multiply/Divide Operations Hardware Real-Time Clock and Calendar (RTCC): • Provides clock, calendar, and alarm functions 2009-2011 Microchip Technology Inc. dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814 and Microcontrollers Direct Memory Access (DMA): • 15-Channel Hardware DMA: ...
Page 4
... Duty cycle, dead time, phase shift and frequency resolution of 8. Seven independent Fault and current-limit inputs - Center-Aligned, Edge-Aligned, Push-Pull, Multi-Phase, Variable Phase, Fixed Off-time, Current Reset and Current Limit modes - Output override control - Output Chopping (gated) mode - Special Event Triggers Preliminary 2009-2011 Microchip Technology Inc. ...
Page 5
... Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking - IPMI support - SMBus support 2009-2011 Microchip Technology Inc. Communication Modules (Continued): • UART (up to four modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode ...
Page 6
... Table 1. Their pinout diagrams appear on the following pages. TABLE 1: dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814 CONTROLLER FAMILIES Device QFN, dsPIC33EP256MU806 64 280 28 TQFP 100 TQFP dsPIC33EP256MU810 280 28 121 XBGA TQFP, dsPIC33EP256MU814 144 280 28 LQFP 100 TQFP dsPIC33EP512MU810 536 52 121 XBGA ...
Page 7
... Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select” 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 2009-2011 Microchip Technology Inc. 48 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 47 PGED2/SOSCI/C3IN3-/RPI61/RC13 ...
Page 8
... Ports” DS70616E-page dsPIC33EP256MU806 for available peripherals and for information on limitations. Preliminary 2009-2011 Microchip Technology Inc. = Pins are tolerant PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 PGED2/SOSCI/C3IN3-/RPI61/RC13 INT0/DMH/RP64/RD0 PMCS1/RPI75/RD11 ASCL1/PMCS2/RPI74/RD10 ASDA1/DPLN/RPI73/RD9 RTCC/DMLN/RPI72/RD8 V SS OSC2/CLKO/RC15 OSC1/RPI60/RC12 V DD D+/RG2 D-/RG3 V USB V BUS USBID/RP99/RF3 ...
Page 9
... Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See for more information. “I/O Ports” 2009-2011 Microchip Technology Inc. = Pins are tolerant dsPIC33EP512MU810 63 62 dsPIC33EP256MU810 for available peripherals and for information on limitations. Preliminary V SS PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 PGED2/SOSCI/C3IN3-/RPI61/RC13 INT0/DMH/RP64/RD0 PMCS1/RPI75/RD11 ...
Page 10
... PIC24EP512GU810 64 63 PIC24EP256GU810 for available peripherals and for information on limitations. Preliminary 2009-2011 Microchip Technology Inc PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 PGED2/SOSCI/C3IN3-/RPI61/RC13 INT0/DMH/RP64/RD0 PMCS1/RPI75/RD11 ASCL1/PMCS2/RPI74/RD10 ASDA1/DPLN/RPI73/RD9 RTCC/DMLN/RPI72/RD8 RPI31/RA15 RPI30/RA14 V SS OSC2/CLKO/RC15 OSC1/RPI60/RC12 V DD TDO/RPI21/RA5 TDI/RPI20/RA4 ASDA2/RPI19/RA3 ASCL2/RPI18/RA2 D+/RG2 D-/RG3 V USB V BUS RP104/RF8 RP98/RF2 USBID/RP99/RF3 Section 11 ...
Page 11
... RE8 RE9 RA0 H RB5 RB4 NC J RB3 RB2 RB7 K RB1 RB0 RA10 L RB6 RA9 AV SS Note 1: Refer to Table 2 for full pin names. 2009-2011 Microchip Technology Inc. dsPIC33EP256MU810 dsPIC33EP512MU810 RE0 RG0 RF1 RE1 RA7 RF0 V RD5 CAP RG14 RA6 NC RD7 RD4 ...
Page 12
... PIC24EPXXXGU810/814 TABLE 2: PIN NAMES: dsPIC33EP256MU810 AND dsPIC33EP512MU810 (1,2) DEVICES Pin Full Pin Name Number A1 AN28/PWM3L/PMD4/RP84/RE4 A2 AN27/PWM2H/PMD3/RPI83/RE3 A3 RP125/RG13 A4 AN24/PWM1L/PMD0/RP80/RE0 A5 RP112/RG0 A6 V 2/RP97/RF1 CMPST Connect A9 RPI76/RD12 A10 DPH/RP66/RD2 A11 V /RP65/RD1 CPCON B1 No Connect B2 RP127/RG15 B3 AN26/PWM2L/PMD2/RP82/RE2 B4 AN25/PWM1H/PMD1/RPI81/RE1 B5 AN23/RPI23/RA7 B6 V 1/RP96/RF0 CMPST B7 V CAP ...
Page 13
... PIC24EPXXXGU810/814 TABLE 2: PIN NAMES: dsPIC33EP256MU810 AND dsPIC33EP512MU810 (1,2) DEVICES (CONTINUED) Pin Full Pin Name Number K4 AN8/PMA6/RPI40/RB8 K5 No Connect K6 RP108/RF12 K7 AN14/PMA1/RPI46/RB14 RP79/RD15 K10 USBID/RP99/RF3 K11 RP98/RF2 L1 PGEC1/AN6/RPI38/RB6 L2 V -/RA9 REF The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See ...
Page 14
... RB13 RB15 RF13 Preliminary = Pins are tolerant RD12 RD2 RD1 RD3 V RC14 SS NC RC13 RD11 RD0 NC RD10 RD8 RD9 RA14 RC12 V RC15 SS RA5 RA3 RA4 V RG2 RA2 USB NC RF8 RG3 RD15 RF3 RF2 RD14 RF4 RF5 2009-2011 Microchip Technology Inc. ...
Page 15
... No Connect The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Note 1: available peripherals and for information on limitations. Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See 2: 2009-2011 Microchip Technology Inc. Pin Number E8 RPI31/RA15 E9 RTCC/DMLN/RPI72/RD8 E10 ...
Page 16
... Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See 2: DS70616E-page 16 Pin Number AN9/PMA7/RPI41/RB9 L5 AN10/CV /PMA13/RPI42/RB10 REF L6 RP109/RF13 L7 AN13/PMA10/RPI45/RB13 L8 AN15/PMA0/RPI47/RB15 L9 RPI78/RD14 L10 SDA2/PMA9/RP100/RF4 L11 SCL2/PMA8/RP101/RF5 Section 11.4 “Peripheral Pin Select” Section 11.0 “I/O Ports” Preliminary 2009-2011 Microchip Technology Inc. Full Pin Name for for more information. ...
Page 17
... Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select” 2: Every I/O port pin (RAx-RKx) can be used as change notification (CNAx-CNKx). See for more information. “I/O Ports” 2009-2011 Microchip Technology Inc. = Pins are tolerant 108 107 106 ...
Page 18
... RH12 100 RPI75/RD11 99 ASCL1/RPI74/RD10 98 ASDA1/DPLN/RPI73/RD9 97 RTCC/DMLN/RPI72/RD8 96 RPI31/RA15 95 RPI30/RA14 94 PMCS1/RK11 93 PMCS2/RK12 OSC2/CLKO/RC15 90 OSC1/RPI60/RC12 TDO/RPI21/RA5 87 TDI/RPI20/RA4 86 ASDA2/RPI19/RA3 85 ASCL2/RPI18/RA2 84 RH11 83 RH10 82 RH9 81 RH8 80 D+/RG2 79 D-/RG3 78 V USB 77 V BUS 76 RP104/RF8 75 RP98/RF2 74 USBID/RP99/RF3 Section 11.4 Section 11.0 “I/O 2009-2011 Microchip Technology Inc. ...
Page 19
... Electrical Characteristics .......................................................................................................................................................... 459 33.0 Packaging Information.............................................................................................................................................................. 531 Appendix A: Revision History............................................................................................................................................................. 551 Index ................................................................................................................................................................................................. 561 The Microchip Web Site ..................................................................................................................................................................... 567 Customer Change Notification Service .............................................................................................................................................. 567 Customer Support .............................................................................................................................................................................. 567 Reader Response .............................................................................................................................................................................. 568 Product Identification System ............................................................................................................................................................ 569 2009-2011 Microchip Technology Inc. Preliminary DS70616E-page 19 ...
Page 20
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70616E-page 20 to receive the most current information on all of our products. Preliminary 2009-2011 Microchip Technology Inc. ...
Page 21
... MCU architecture. Figure 1-1 illustrates a general block diagram of the core and peripheral modules dsPIC33EPXXXMU806/810/814 PIC24EPXXXGU810/814 families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. 2009-2011 Microchip Technology Inc. in and contain in the and Preliminary DS70616E-page 21 ...
Page 22
... Timers DCI SPI4 Preliminary X Data Bus PORTA 16 Data Latch X Data PORTB RAM 24 16 Address Latch 16 16 PORTC X RAGU X WAGU PORTD EA MUX PORTE 16 24 PORTF PORTG 16 Divide PORTH Support PORTJ 16 PORTK Remappable I2C1, Pins I2C2 UART1- UART4 2009-2011 Microchip Technology Inc. ...
Page 23
... PPS = Peripheral Pin Select This pin is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: AV must be connected at all times 2009-2011 Microchip Technology Inc. PPS Description No Analog input channels. No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
Page 24
... Yes SPI4 data out. Yes SPI4 slave synchronization or frame pulse I/O. No Alternate synchronous serial clock input/output for I2C1. No Alternate synchronous serial data input/output for I2C1. Analog = Analog input O = Output TTL = TTL input buffer Preliminary P = Power I = Input 2009-2011 Microchip Technology Inc. ...
Page 25
... ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select This pin is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: AV must be connected at all times 2009-2011 Microchip Technology Inc. PPS Description No Synchronous serial clock input/output for I2C2. No Synchronous serial data input/output for I2C2. No Alternate synchronous serial clock input/output for I2C2 ...
Page 26
... Master Clear (Reset) input. This pin is an active-low Reset to the device. No Positive supply for analog modules. This pin must be connected at all times. No Ground reference for analog modules. Analog = Analog input O = Output TTL = TTL input buffer Preliminary . Power I = Input 2009-2011 Microchip Technology Inc. ...
Page 27
... ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select This pin is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: AV must be connected at all times 2009-2011 Microchip Technology Inc. PPS Description No Positive supply for peripheral logic and I/O pins. No CPU logic filter capacitor connection. No Ground reference for logic and I/O pins ...
Page 28
... Section 27. “Programmable Cyclic Redundancy Check (CRC)” (DS70346) • Section 28. “Parallel Master Port (PMP)” (DS70576) • Section 29. “Real-Time Clock and Calendar (RTCC)” (DS70584) • Section 30. “Device Configuration” (DS70618) DS70616E-page 28 product page web site from the 2 C™)” (DS70330) Preliminary 2009-2011 Microchip Technology Inc. ...
Page 29
... ADC voltage reference source. The voltage difference between AV DD exceed 300 mV at any time during operation or start-up. 2009-2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as V and AV is required. ...
Page 30
... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2009-2011 Microchip Technology Inc. is ...
Page 31
... Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. 2009-2011 Microchip Technology Inc. FIGURE 2-3: Main Oscillator Guard Ring Guard Trace Secondary Oscillator 2 ...
Page 32
... PIC24EPXXXGU810/814 NOTES: DS70616E-page 32 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 33
... The instruction set includes many addressing modes and was designed for optimum C compiler efficiency. 2009-2011 Microchip Technology Inc. 3.3 Data Space Addressing The base data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory ...
Page 34
... ADC1, ECAN1, Capture ADC2 Compare ECAN2 SPI1- USB OTG Timers DCI SPI4 Preliminary X Data Bus 16 16 Data Latch X Data (1) RAM 24 16 Address Latch RAGU X WAGU EA MUX Divide Support 16-bit ALU 16 I2C1, I2C2 I/O Ports UART1- UART4 2009-2011 Microchip Technology Inc. ...
Page 35
... DOENDH , DOENDL CORCON This register is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: The DOSTARTH and DOSTARTL registers are read-only. 2: 2009-2011 Microchip Technology Inc. In addition to the registers contained in the programmer’s model, the dsPIC33EPXXXMU806/810/ for the 814 and PIC24EPXXXGU810/814 devices contain and control ...
Page 36
... X Data Space Read Page Address X Data Space Write Page Address Repeat Loop Counter (1) DO Loop Counter and Stack (1) DO Loop Start Address and Stack (1) DO Loop End Address and Stack CPU Core Control Register Status Register 2009-2011 Microchip Technology Inc. ...
Page 37
... A data write to the SR register can modify the SA and SB bits by either a data write to SA and clearing the SAB bit. To avoid a possible bit write race condition, the SA and SB bits should not be modified using bit operations. 2009-2011 Microchip Technology Inc. R/W-0 R/C-0 (1,4) ...
Page 38
... A data write to the SR register can modify the SA and SB bits by either a data write to SA and clearing the SAB bit. To avoid a possible bit write race condition, the SA and SB bits should not be modified using bit operations. DS70616E-page 38 (2) Preliminary 2009-2011 Microchip Technology Inc. ...
Page 39
... CPU interrupt priority level less This bit is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 3: 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 (1) (1,2) US<1:0> EDT ...
Page 40
... Fractional mode enabled for DSP multiply This bit is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 3: DS70616E-page 40 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 41
... W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 2009-2011 Microchip Technology Inc. 3.8 DSP Engine (dsPIC33EPXXXMU806/810/814 and ...
Page 42
... PIC24EPXXXGU810/814 NOTES: DS70616E-page 42 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 43
... Reset Address Device Configuration DEVID (2 Words) Memory areas are not shown to scale. Note 1: Reset location is controlled by Reset Target Vector Select bit (RSTPRI). See 2: 2009-2011 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33EPXXXMU806/810/814 PIC24EPXXXGU810/814 devices is 4M instructions. The space is addressable by a 24-bit value derived ...
Page 44
... Flash Reset location is used. A more detailed discussion of the interrupt vector tables is provided in Table”. least significant word Instruction Width Preliminary and devices reserve the Section 7.1 “Interrupt Vector PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 2009-2011 Microchip Technology Inc. ...
Page 45
... Data byte writes only write to the corresponding side of the array or register that matches the byte address. 2009-2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so and care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
Page 46
... X Data RAM (X) 0x7FFE 0x8000 0x8FFE 0x9000 Y Data RAM (Y) 0xCFFE 0xD000 DMA Dual Port RAM (Y) 0xDFFE 0xE000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space Far Data Space Optionally Mapped into Program Memory 2009-2011 Microchip Technology Inc. ...
Page 47
... Kbyte SFR Space 0x0FFF 0x1001 0x1FFF 0x2001 0x7FFF 0x8001 52 Kbyte SRAM Space 0xCFFF 0xD001 0xDFFF 0xE001 0xFFFF 2009-2011 Microchip Technology Inc. LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE 0x2000 0x7FFE 0x8000 X Data RAM (X) 0xCFFE 0xD000 ...
Page 48
... SFR Space 0x0FFE 0x1000 0x1FFE 0x2000 X Data RAM (X) 0x4FFE 0x5000 Y Data RAM (Y) 0x6FFE 0x7000 DMA Dual Port RAM (Y) 0x7FFE 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space Far Data Space Optionally Mapped into Program Memory 2009-2011 Microchip Technology Inc. ...
Page 49
... Address 0x0001 4 Kbyte SFR Space 0x0FFF 0x1001 0x1FFF 0x2001 28 Kbyte SRAM Space 0x6FFF 0x7001 0x7FFF 0x8001 0xFFFF 2009-2011 Microchip Technology Inc. LSb 16 bits Address MSb LSb 0x0000 SFR Space 0x0FFE 0x1000 0x1FFE 0x2000 X Data RAM (X) 0x6FFE 0x7000 DMA Dual Port RAM ...
Page 50
... Note 1: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application PIC24EPXXXGU810/814 devices, DMA RAM is located at the end of X data RAM and is part of X data space. Bit-Reversed Bit-Reversed Preliminary and 2009-2011 Microchip Technology Inc. ...
Page 51
TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0000 W0 0002 W1 0004 W2 0006 W3 0008 W4 000A W5 000C W6 000E W7 0010 W8 0012 ...
Page 52
TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0042 0044 CORCON VAR — US<1:0> 0046 XMODEN YMODEN MODCON — — 0048 ...
Page 53
TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name 0000 W0 0002 W1 0004 W2 0006 W3 0008 W4 000A W5 000C W6 000E W7 0010 W8 0012 ...
Page 54
TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 T6IF DMA4IF PMPIF OC8IF IFS3 ...
Page 55
TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IPC17 0862 — C2TXIP<2:0> IPC18 0864 — QEI2IP<2:0> IPC20 0868 — U3TXIP<2:0> IPC21 086A — U4EIP<2:0> IPC22 086C ...
Page 56
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 T6IF DMA4IF PMPIF OC8IF ...
Page 57
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IPC17 0862 — C2TXIP<2:0> IPC18 0864 — QEI2IP<2:0> IPC20 0868 — U3TXIP<2:0> IPC21 086A — U4EIP<2:0> IPC22 086C ...
Page 58
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 T6IF DMA4IF PMPIF OC8IF IFS3 ...
Page 59
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IPC17 0862 — C2TXIP<2:0> IPC18 0864 — QEI2IP<2:0> IPC20 0868 — U3TXIP<2:0> IPC21 086A — U4EIP<2:0> IPC22 086C ...
Page 60
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF IFS1 0802 U2TXIF U2RXIF INT2IF T5IF IFS2 0804 T6IF DMA4IF PMPIF OC8IF IFS3 ...
Page 61
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name IPC21 086A — U4EIP<2:0> IPC22 086C — SPI3IP<2:0> IPC23 086E — — — — IPC29 087A — DMA9IP<2:0> ...
Page 62
TABLE 4-7: TIMER1 THROUGH TIMER9 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 ...
Page 63
TABLE 4-8: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 16 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1CON1 0140 — — ICSIDL IC1CON2 0142 — — — — 0144 IC1BUF IC1TMR 0146 IC2CON1 0148 — ...
Page 64
TABLE 4-8: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 16 REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 018C IC10BUF IC10TMR 018E IC11CON1 0190 — — ICSIDL IC11CON2 0192 — — — — 0194 IC11BUF ...
Page 65
TABLE 4-9: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0900 OC1CON1 — — OCSIDL OCTSEL<2:0> OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0904 OC1R 0906 OC1TMR 0908 ...
Page 66
TABLE 4-9: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0946 OC8CON1 — — OCSIDL OCTSEL<2:0> OC8CON2 0948 FLTMD FLTOUT FLTTRIEN OCINV OC8RS 094A OC8R 094C OC8TMR ...
Page 67
TABLE 4-9: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 OC15CON1 098C — — OCSIDL OCTSEL<2:0> OC15CON2 098E FLTMD FLTOUT FLTTRIEN OCINV OC15RS 0990 OC15R 0992 OC15TMR ...
Page 68
TABLE 4-10: PWM REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 0C00 PTEN — PTSIDL SESTAT PTCON2 0C02 — — — — PTPER 0C04 SEVTCMP 0C06 MDC 0C0A STCON 0C0E ...
Page 69
TABLE 4-12: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON2 0C42 PENH PENL POLH POLL FCLCON2 0C44 IFLTMOD CLSRC<4:0> PDC2 0C46 ...
Page 70
TABLE 4-14: PWM GENERATOR 4 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PWMCON4 0C80 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON4 0C82 PENH PENL POLH POLL FCLCON4 0C84 IFLTMOD CLSRC<4:0> PDC4 0C86 ...
Page 71
TABLE 4-16: PWM GENERATOR 6 REGISTER MAP FOR dsPIC33EPXXXMU810/814 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PWMCON6 0CC0 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON6 0CC2 PENH PENL POLH POLL FCLCON6 0CC4 IFLTMOD CLSRC<4:0> PDC6 0CC6 ...
Page 72
TABLE 4-18: QEI1 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 QEI1CON 01C0 QEIEN — QEISIDL QEI1IOC 01C2 QCAPEN FLTREN QFDIV<2:0> QEI1STAT 01C4 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN ...
Page 73
TABLE 4-19: QEI2 REGISTER MAP FOR dsPIC33EPXXXMU806/810/814 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 QEI2CON 05C0 QEIEN — QEISIDL QEI2IOC 05C2 QCAPEN FLTREN QFDIV<2:0> QEI2STAT 05C4 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN ...
Page 74
TABLE 4-20: I2C1 and I2C2 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0200 I2C1RCV — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
Page 75
TABLE 4-21: UART1, UART2, UART3, and UART4 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name 0220 U1MODE UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 ...
Page 76
TABLE 4-22: SPI1, SPI2, SPI3, and SPI4 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 0240 — — SPI1STAT SPIEN SPISIDL 0242 — — — SPI1CON1 DISSCK DISSDO MODE16 0244 — SPI1CON2 FRMEN SPIFSD FRMPOL ...
Page 77
TABLE 4-23: ADC1 and ADC2 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
Page 78
TABLE 4-23: ADC1 and ADC2 REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADC2BUF9 0352 ADC2BUFA 0354 ADC2BUFB 0356 ADC2BUFC 0358 ADC2BUFD 035A ADC2BUFE 035C ADC2BUFF 035E AD2CON1 0360 ADON — ADSIDL ADDMABM AD2CON2 ...
Page 79
TABLE 4-24: DCI REGISTER MAP File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name DCICON1 0280 DCIEN — DCISIDL — DCICON2 0282 — — — — DCICON3 0284 — — — — DCISTAT 0286 — — — — ...
Page 80
TABLE 4-25: USB OTG REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1OTGIR 0488 — — — — — U1OTGIE 048A — — — — — U1OTGSTAT 048C — — — — — ...
Page 81
TABLE 4-25: USB OTG REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1EP5 04EA — — — — — U1EP6 04EC — — — — — U1EP7 04EE — — — — ...
Page 82
TABLE 4-26: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — — C1VEC 0404 — — — ...
Page 83
TABLE 4-28: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 — 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 SID<10:3> C1RXM0EID ...
Page 84
TABLE 4-28: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0> (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> C1RXF14SID 0478 SID<10:3> C1RXF14EID 047A EID<15:8> C1RXF15SID 047C SID<10:3> C1RXF15EID 047E EID<15:8> ...
Page 85
TABLE 4-29: ECAN2 REGISTER MAP WHEN WIN (C2CTRL<0> File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2CTRL1 0500 — — CSIDL ABAT C2CTRL2 0502 — — — — C2VEC 0504 — — — ...
Page 86
TABLE 4-31: ECAN2 REGISTER MAP WHEN WIN (C2CTRL<0> File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — 0500- 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F11BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID 0530 SID<10:3> C2RXM0EID ...
Page 87
TABLE 4-31: ECAN2 REGISTER MAP WHEN WIN (C2CTRL<0> (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2RXF13SID 0574 SID<10:3> C2RXF13EID 0576 EID<15:8> C2RXF14SID 0578 SID<10:3> C2RXF14EID 057A EID<15:8> C2RXF15SID 057C SID<10:3> C2RXF15EID 057E EID<15:8> ...
Page 88
TABLE 4-32: PARALLEL MASTER/SLAVE PORT REGISTER MAP Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PMMODE 0602 BUSY IRQM<1:0> INCM<1:0> PMADDR (1) 0604 CS2 CS1 (1) PMDOUT1 0604 PMDOUT2 0606 PMDIN1 0608 ...
Page 89
TABLE 4-34: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME AMASK<3:0> RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC x = unknown value on ...
Page 90
TABLE 4-36: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 0680 — — RPOR1 0682 — — RPOR2 0684 — — RPOR3 0686 — — RPOR4 ...
Page 91
TABLE 4-37: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 06A0 — INT1R<6:0> RPINR1 06A2 — INT3R<6:0> RPINR2 06A4 — — — — RPINR3 06A6 — ...
Page 92
TABLE 4-37: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR39 06EE — DTCMP3R<6:0> RPINR40 06F0 — DTCMP5R<6:0> RPINR41 06F2 — DTCMP7R<6:0> RPINR42 06F4 — FLT6R<6:0> ...
Page 93
TABLE 4-38: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 RPINR0 06A0 — RPINR1 06A2 — RPINR2 06A4 — — — — RPINR3 06A6 — RPINR4 06A8 ...
Page 94
TABLE 4-38: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 RPINR39 06EE — DTCMP3R<6:0> RPINR40 06F0 — DTCMP5R<6:0> RPINR41 06F2 — — — — RPINR42 06F4 ...
Page 95
TABLE 4-39: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 RPINR0 06A0 — RPINR1 06A2 — RPINR2 06A4 — — — — RPINR3 06A6 — RPINR4 06A8 ...
Page 96
TABLE 4-39: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 RPINR39 06EE — DTCMP3R<6:0> RPINR40 06F0 — — — — RPINR42 06F4 — RPINR43 06F6 — ...
Page 97
TABLE 4-40: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 06A0 — RPINR1 06A2 — RPINR2 06A4 — — — — RPINR3 06A6 — RPINR4 06A8 ...
Page 98
TABLE 4-41: REFERENCE CLOCK REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 REFOCON 074E ROON — ROSSLP ROSEL x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in ...
Page 99
TABLE 4-44: PMD REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name PMD1 0760 T5MD T4MD T3MD T2MD PMD2 0762 IC8MD IC7MD IC6MD IC5MD PMD3 0764 T9MD T8MD T7MD T6MD PMD4 0766 ...
Page 100
TABLE 4-46: PMD REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name PMD1 0760 T5MD T4MD T3MD T2MD PMD2 0762 IC8MD IC7MD IC6MD IC5MD IC4MD PMD3 0764 T9MD T8MD T7MD T6MD PMD4 ...
Page 101
TABLE 4-48: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0A80 CMSIDL — — — CVRCON 0A82 — — — — CM1CON 0A84 CON COE CPOL — CM1MSKSRC 0A86 — — — — ...
Page 102
TABLE 4-49: DMAC REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0B00 CHEN SIZE DIR HALF DMA0REQ 0B02 FORCE — — — DMA0STAL 0B04 DMA0STAH 0B06 — — — — DMA0STBL 0B08 DMA0STBH 0B0A ...
Page 103
TABLE 4-49: DMAC REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DMA4STBH 0B4A — — — — DMA4PAD 0B4C DMA4CNT 0B4E — — DMA5CON 0B50 CHEN SIZE DIR HALF DMA5REQ 0B52 FORCE — — ...
Page 104
TABLE 4-49: DMAC REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DMA9STAH 0B96 — — — — DMA9STBL 0B98 DMA9STBH 0B9A — — — — DMA9PAD 0B9C DMA9CNT 0B9E — — DMA10CON 0BA0 CHEN ...
Page 105
TABLE 4-49: DMAC REGISTER MAP (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DMA14REQ 0BE2 FORCE — — — DMA14STAL 0BE4 DMA14STAH 0BE6 — — — — DMA14STBL 0BE8 DMA14STBH 0BEA — — — — DMA14PAD ...
Page 106
TABLE 4-50: PORTA REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 0E00 TRISA15 TRISA14 — — PORTA 0E02 RA15 RA14 — — LATA 0E04 LATA15 LATA14 — — ...
Page 107
TABLE 4-53: PORTC REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY File Addr, Bit 15 Bit 14 Bit 13 Bit 12 Name TRISC 0E20 TRISC15 TRISC14 TRISC13 TRISC12 PORTC 0E22 RC15 RC14 RC13 RC12 LATC 0E24 LATC15 LATC14 LATC13 LATC12 ODCC 0E26 ...
Page 108
TABLE 4-56: PORTE REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISE 0E40 — — — — PORTE 0E42 — — — — LATE 0E44 — — — — ...
Page 109
TABLE 4-59: PORTF REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISF 0E50 — — — — PORTF 0E52 — — — — LATF 0E54 — — — — ODCF 0E56 ...
Page 110
TABLE 4-62: PORTH REGISTER MAP FOR dsPIC33EPXXXMU814 AND PIC24EPXXXGU814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISH 0E70 TRISH15 TRISH14 TRISH13 TRISH12 PORTH 0E72 RH15 RH14 RH13 RH12 LATH 0E74 LATH15 LATH14 LATH13 LATH12 ...
Page 111
TABLE 4-64: PORTK REGISTER MAP FOR dsPIC33EPXXXMU814 AND PIC24EPXXXGU814 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISK 0E90 TRISK15 TRISK14 TRISK13 TRISK12 PORTK 0E92 RK15 RK14 RK13 RK12 LATK 0E94 LATK15 LATK14 LATK13 LATK12 ...
Page 112
... EA<15>=1, DSWPAG<8:0> is concatenated onto EA<14:0> to form the 24-bit EDS write address. 16-bit EDS access 0 EA<15> Y DSRPAG<9> DSRPAG<9> Select DSRPAG DSRPAG<8:0> bits 15 bits 24-bit EDS EA Preliminary Figure 4-1. Byte Select EA EA Byte Select 2009-2011 Microchip Technology Inc. ...
Page 113
... DSRPAG of 0x200 or greater. Only reads from PS are supported using the DSRPAG. Writes to PS are not supported, so DSWPAG is dedicated to DS, including EDS, only. The data space and EDS can be read from and written to using DSRPAG and DSWPAG, respectively. 2009-2011 Microchip Technology Inc. 16-bit EDS access EA 0 EA<15> ...
Page 114
EXAMPLE 4-3: PAGED DATA MEMORY SPACE Local Data Space DS_Addr<14:0> 0x0000 0x7FFF 0x0000 0x7FFF DS_Addr<15:0> 0x0000 0x0000 SFR Registers 0x0FFF 0x7FFF 0x1000 0x0000 KByte RAM 0x7FFF 0x7FFF 0x8000 32 KByte EDS Window 0x0000 0xFFFF 0x7FFF 0x0000 0x7FFF ...
Page 115
... Pseudo-linear addressing is not supported for large offsets. 4: 2009-2011 Microchip Technology Inc. In general, when an overflow is detected, the DSxPAG register is incremented, and the EA<15> bit is set to keep the base address within the EDS or PSV window. When an underflow is detected, the DSxPAG register is decremented, and the EA< ...
Page 116
... Memory” (DS70613) of the “dsPIC33E/ PIC24E Family Reference Manual”. (PAGE 0) 0x008000 PAGE 1 0x010000 PAGE 2 0x018000 PAGE 3 0xFE8000 PAGE 1FD 0xFF0000 PAGE 1FE 0xFF8000 PAGE 1FF Preliminary 2009-2011 Microchip Technology Inc. DSRPAG = 0x01 or DSRPAG<9> EDS EA Address (24-bits) (DSRPAG<8:0>, EA<14:0>) (DSWPAG<8:0>, EA<14:0>) ...
Page 117
... FIGURE 4-8: ARBITER ARCHITECTURE DPSRAM MSTRPR<15:0> 2009-2011 Microchip Technology Inc. respectively (M1 is reserved and cannot be used). The user application may raise or lower the priority of the masters to be above that of the CPU by setting the appropriate bits in the EDS Bus Master Priority Control (MSTRPR) register ...
Page 118
... Not all instructions support all the Note: addressing modes given above. Individ- ual instructions can support different subsets of these addressing modes. Preliminary CALL STACK FRAME 0 CALL SUBR PC<15:1> W15 (before CALL) PC<22:16> <Free Word> W15 (after CALL) Table 4-68 form the 2009-2011 Microchip Technology Inc. ...
Page 119
... Note: addressing modes given above. Individual instructions may support different subsets of these addressing modes. 2009-2011 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). ...
Page 120
... MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary 2009-2011 Microchip Technology Inc. between the Table 4-1). Modulo Addressing is ...
Page 121
... Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment 2009-2011 Microchip Technology Inc. If the length of a bit-reversed buffer the last ‘N’ bits of the data buffer start address must be zeros. ...
Page 122
... TABLE 4-69: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70616E-page 122 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal 2009-2011 Microchip Technology Inc. ...
Page 123
... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. 2009-2011 Microchip Technology Inc. Table instructions allow an application to read or write to small areas of the program memory. This capability ...
Page 124
... TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. Preliminary Section 5.0 “Flash 2009-2011 Microchip Technology Inc. ...
Page 125
... Program Counter Using 1/0 Table Instruction User/Configuration Space Select 2009-2011 Microchip Technology Inc. pin pairs: PGECx/PGEDx), and three other lines for power (V DD This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed ...
Page 126
... Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles = 1 0.05 – 1 0.00375 – (Register 5-1) controls which 5- write-only register that is the user application must 2009-2011 Microchip Technology Inc. ...
Page 127
... All other combinations of NVMOP<3:0> are unimplemented. 3: The entire segment is erased with the exception of IVT. 4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. 5: Two adjacent words are programmed during execution of this operation. 6: 2009-2011 Microchip Technology Inc. (1) R/W-0 U-0 (2) NVMSIDL — (1) ...
Page 128
... Bit is cleared U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-x R/W-x bit Bit is unknown R/W-x R/W-x bit 8 R/W-x ...
Page 129
... DD Trap Conflict Illegal Opcode Uninitialized W Register Security Reset Configuration Mismatch 2009-2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of Reset will make the SYSRST sig- nal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected ...
Page 130
... SWDTEN bit setting. DS70616E-page 130 (1) U-0 R/W-0 — VREGSF R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
Page 131
... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not Note 1: cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the 2: SWDTEN bit setting. 2009-2011 Microchip Technology Inc. (1) (CONTINUED) Preliminary DS70616E-page 131 ...
Page 132
... PIC24EPXXXGU810/814 NOTES: DS70616E-page 132 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 133
... Eight user-selectable priority levels • Interrupt Vector Table (IVT) with a unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Fixed interrupt entry and return latencies 2009-2011 Microchip Technology Inc. 7.1 Interrupt Vector Table The dsPIC33EPXXXMU806/810/814 ...
Page 134
... Flash Reset location is used. DS70616E-page 134 (1) 0x000000 (1) 0x000002 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 Reserved 0x000012 0x000014 0x000016 : : : : : : 0x00007C 0x00007E 0x000080 : : : : : : 0x0000FC 0x0000FE 0x000100 0x000102 0x000104 : : : : : : 0x0001FC 0x0001FE 0x000200 Preliminary See Table 7-1 for Interrupt Vector details 2009-2011 Microchip Technology Inc. ...
Page 135
... IC4 – Input Capture 4 IC5 – Input Capture 5 IC6 – Input Capture 6 OC5 – Output Compare 5 OC6 – Output Compare 6 This interrupt source is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: 2009-2011 Microchip Technology Inc. Vector IVT IRQ Number Address Highest Natural Order Priority ...
Page 136
... IPC17<2:0> IEC4<5> IPC17<6:4> IEC4<6> IPC17<10:8> IEC4<7> IPC17<14:12> — — — IEC4<9> IPC18<6:4> — — — IEC4<11> IPC18<14:12> — — — IEC5<1> IPC20<6:4> IEC5<2> IPC20<10:8> IEC5<3> IPC20<14:12> — — — — — — IEC5<6> IPC21<10:8> IEC5<7> IPC21<14:12> 2009-2011 Microchip Technology Inc. ...
Page 137
... OC15 – Output Compare 15 IC15 – Input Capture 15 OC16 – Output Compare 16 IC16 – Input Capture 16 ICD – ICD Application Reserved This interrupt source is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: 2009-2011 Microchip Technology Inc. Vector IVT IRQ Number Address 96 88 0x0000C4 IFS5<8> ...
Page 138
... CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in through Register 7-7 Preliminary 7-1. For example, the INT0 (External Register 7-3 in the following pages. 2009-2011 Microchip Technology Inc. ...
Page 139
... Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority 2: Level. The value in parentheses indicates the IPL, if IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15> 2009-2011 Microchip Technology Inc. (1) R/W-0 R/C-0 SB OAB ...
Page 140
... US<1:0> EDT R/W-0 R/C-0 (2) ACCSAT IPL3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Register 3-2: “CORCON: Core Control Preliminary R-0 R-0 R-0 DL<2:0> bit 8 R-0 R/W-0 R/W-0 SFA RND IF bit Bit is unknown Register”. 2009-2011 Microchip Technology Inc. ...
Page 141
... DMAC trap has occurred 0 = DMAC trap has not occurred bit 4 MATHERR: Math Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred This bit is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 (1) (1) (1) COVAERR COVBERR ...
Page 142
... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ This bit is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: DS70616E-page 142 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 143
... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge 2009-2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 144
... U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — ...
Page 145
... CPU Interrupt Priority Level is 0 bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt bits 11111111 = Interrupt vector pending is number 263 • • • 00000001 = Interrupt vector pending is number 9 00000000 = Interrupt vector pending is number 8 2009-2011 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
Page 146
... PIC24EPXXXGU810/814 NOTES: DS70616E-page 146 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 147
... CPU and DMA controller can write and read to/from FIGURE 8-1: DMA CONTROLLER PERIPHERAL 2009-2011 Microchip Technology Inc. addresses within data space without interference, such as CPU stalls, resulting in maximized, real-time performance. Alternatively, DMA operation and data transfer to/from the memory and peripherals are not impacted by CPU processing ...
Page 148
... Microchip Technology Inc. ...
Page 149
... DMA CONTROLLER BLOCK DIAGRAM SRAM Arbiter DPSRAM PORT 1 PORT 2 SRAM X-Bus CPU Note: CPU and DMA address buses are not shown for clarity. 2009-2011 Microchip Technology Inc. DMAxPAD Register DMAxREQ Register (Values to Read from IRQSEL<7:0> Bits Peripheral) — 01011001 0x0440 (C1RXD) 00100010 — ...
Page 150
... R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ‘ ’ 0 ‘ ’ 0 Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
Page 151
... SPI3 – Transfer Done 01111011 = SPI4 – Transfer Done The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the Note 1: forced DMA transfer is complete or the channel is disabled (CHEN = 0). 2009-2011 Microchip Technology Inc. IRQ SELECT REGISTER X U-0 U-0 U-0 — ...
Page 152
... START ADDRESS REGISTER A (LOW) X R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 ...
Page 153
... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary Start Address Offset bits (source or destination) 2009-2011 Microchip Technology Inc. START ADDRESS REGISTER B (HIGH) X U-0 R/W-0 U-0 — — — R/W-0 R/W-0 R/W-0 STB< ...
Page 154
... TRANSFER COUNT REGISTER X R/W-0 R/W-0 R/W-0 (2) CNT<13:8> R/W-0 R/W-0 R/W-0 (2) CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary 2009-2011 Microchip Technology Inc. (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 155
... R-0 R-0 R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits 2009-2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R-0 R-0 R-0 DSADR<23:16> Unimplemented bit, read as ‘0’ ...
Page 156
... DS70616E-page 156 R-0 R-0 R-0 PWCOL12 PWCOL11 PWCOL10 R-0 R-0 R-0 PWCOL4 PWCOL3 PWCOL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. R-0 R-0 PWCOL9 PWCOL8 bit 8 R-0 R-0 PWCOL1 PWCOL0 bit Bit is unknown ...
Page 157
... Write collision detected write collision detected bit 1 PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected write collision detected 2009-2011 Microchip Technology Inc. Preliminary DS70616E-page 157 ...
Page 158
... DS70616E-page 158 R-0 R-0 R-0 RQCOL12 RQCOL11 RQCOL10 R-0 R-0 R-0 RQCOL4 RQCOL3 RQCOL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. R-0 R-0 RQCOL9 RQCOL8 bit 8 R-0 R-0 RQCOL1 RQCOL0 bit Bit is unknown ...
Page 159
... RQCOL1: Channel 1 Transfer Request Collision Flag bit 1 = User FORCE and Interrupt-based request collision detected request collision detected bit 0 RQCOL0: Channel 0 Transfer Request Collision Flag bit 1 = User FORCE and Interrupt-based request collision detected request collision detected 2009-2011 Microchip Technology Inc. Preliminary DS70616E-page 159 ...
Page 160
... Last data transfer was handled by Channel 0 DS70616E-page 160 U-0 U-0 U-0 — — — U-0 R-1 R-1 — LSTCH<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R-1 R-1 bit Bit is unknown ...
Page 161
... PPST4: Channel 4 Ping-Pong Mode Status Flag bit 1 = DMASTB4 register selected 0 = DMASTA4 register selected bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMASTB3 register selected 0 = DMASTA3 register selected 2009-2011 Microchip Technology Inc. R-0 R-0 R-0 PPST12 PPST11 PPST10 R-0 R-0 ...
Page 162
... DMASTB2 register selected 0 = DMASTA2 register selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMASTB1 register selected 0 = DMASTA1 register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMASTB0 register selected 0 = DMASTA0 register selected DS70616E-page 162 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 163
... If the Oscillator is used with modes, an external parallel resistor with the value of 1 M must be connected. 2: See Figure 9-3 for APLL details. 3: 2009-2011 Microchip Technology Inc. The dsPIC33EPXXXMU806/810/814 PIC24EPXXXGU810/814 oscillator system provides: • Four external and internal oscillator options • Auxiliary oscillator that provides clock source to the USB module • ...
Page 164
... CY DEVICE OPERATING FREQUENCY F = Fosc/2 CY provides the relation between input ) and output frequency ( OSC provides the relation between input ) and VCO frequency ( VCO < 340 < 120 MHz OSC F OSC ÷ N2 PLLPOST<2:0> PLLPOST 1 2009-2011 Microchip Technology Inc. ...
Page 165
... Primary Oscillator (EC) Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL) Fast RC Oscillator (FRC) OSC2 pin function is determined by the OSCIOFNC Configuration bit. Note 1: This is the default oscillator mode for an unprogrammed (erased) device. 2: 2009-2011 Microchip Technology Inc. < 5.5 MHz AREF PFD VCO ÷ M ...
Page 166
... This register resets only on a Power-on Reset (POR). 3: DS70616E-page 166 (1,3) R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) OSC (2) ) OSC Preliminary 2009-2011 Microchip Technology Inc. R/W-y R/W-y (2) NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 167
... This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. This register resets only on a Power-on Reset (POR). 3: 2009-2011 Microchip Technology Inc. (1,3) (CONTINUED) Preliminary DS70616E-page 167 ...
Page 168
... DOZEN bit is ignored. DS70616E-page 168 (2) R/W-1 R/W-0 R/W-0 (3) (1,4) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (1,4) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
Page 169
... DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to 3: DOZE<2:0> are ignored. The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to 4: set the DOZEN bit is ignored. 2009-2011 Microchip Technology Inc. (2) (CONTINUED) Preliminary DS70616E-page 169 ...
Page 170
... This register is reset only on a Power-on Reset (POR). Note 1: DS70616E-page 170 (1) U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 171
... Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) This register resets only on a Power-on Reset (POR). Note 1: 2009-2011 Microchip Technology Inc. (1) U-0 U-0 U-0 — — — R/W-0 ...
Page 172
... This register resets only on a Power-on Reset (POR). Note 1: DS70616E-page 172 R/W-0 R/W-0 R/W-0 AOSCMD<1:0> ASRCSEL U-0 U-0 R/W-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. (1) R/W-0 U-0 FRCSEL — bit 8 R/W-0 R/W-0 APLLPRE<2:0> bit Bit is unknown ...
Page 173
... APLLDIV<2:0>: PLL Feedback Divisor bits (PLL Multiplier Ratio) 111 = 24 110 = 21 101 = 20 100 = 19 011 = 18 010 = 17 001 = 16 000 = 15 (default) This register resets only on a Power-on Reset (POR). Note 1: 2009-2011 Microchip Technology Inc. (1) U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — ...
Page 174
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) pin (1) Section 11.4 “Peripheral Pin Select” Preliminary R/W-0 R/W-0 R/W-0 (1) RODIV<3:0> bit 8 U-0 U-0 U-0 — — — bit Bit is unknown for more information. 2009-2011 Microchip Technology Inc. ...
Page 175
... Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode 2009-2011 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes The dsPIC33EPXXXMU806/810/814 PIC24EPXXXGU810/814 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 176
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). Preliminary There are eight possible ® DSC 2009-2011 Microchip Technology Inc. ...
Page 177
... U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled This bit is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) T2MD T1MD QEI1MD R/W-0 ...
Page 178
... ECAN2 module is enabled bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled This bit is available on dsPIC33EPXXXMU806/810/814 devices only. Note 1: DS70616E-page 178 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 179
... OC6MD: Output Compare 6 Module Disable bit 1 = Output Compare 6 module is disabled 0 = Output Compare 6 module is enabled bit 4 OC5MD: Output Compare 5 Module Disable bit 1 = Output Compare 5 module is disabled 0 = Output Compare 5 module is enabled 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 IC5MD IC4MD IC3MD R/W-0 ...
Page 180
... Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70616E-page 180 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 181
... I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 AD2MD: ADC2 Module Disable bit 1 = ADC2 module is disabled 0 = ADC2 module is enabled This bit is available in dsPIC33EPXXXMU806/810/814 devices only. Note 1: 2009-2011 Microchip Technology Inc. R/W-0 U-0 T6MD — CMPMD U-0 R/W-0 (1) — ...
Page 182
... DS70616E-page 182 U-0 U-0 U-0 — — — U-0 R/W-0 U-0 — REFOMD — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 R/W-0 — USB1MD bit Bit is unknown ...
Page 183
... OC15 module is enabled bit 5 OC14MD: OC14 Module Disable bit 1 = OC14 module is disabled 0 = OC14 module is enabled bit 4 OC13MD: OC13 Module Disable bit 1 = OC13 module is disabled 0 = OC13 module is enabled 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 IC13MD IC12MD IC11MD R/W-0 R/W-0 R/W-0 ...
Page 184
... OC11MD: OC11 Module Disable bit 1 = OC11 module is disabled 0 = OC11 module is enabled bit 1 OC10MD: OC10 Module Disable bit 1 = OC10 module is disabled 0 = OC10 module is enabled bit 0 OC9MD: OC9 Module Disable bit 1 = OC9 module is disabled 0 = OC9 module is enabled DS70616E-page 184 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 185
... SPI4MD: SPI4 Module Disable bit 1 = SPI4 module is disabled 0 = SPI4 module is enabled bit 0 SPI3MD: SPI3 Module Disable bit 1 = SPI3 module is disabled 0 = SPI3 module is enabled This bit is available in dsPIC33EPXXXMU806/810/814 devices only. Note 1: 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) (1) (1) PWM5MD PWM4MD ...
Page 186
... U-0 U-0 — — — R/W-0 U-0 U-0 DMA0MD DMA1MD — — DMA2MD DMA3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2009-2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 187
... DMA1 module is disabled 0 = DMA1 module is enabled DMA2MD: DMA2 Module Disable bit 1 = DMA2 module is disabled 0 = DMA2 module is enabled DMA3MD: DMA3 Module Disable bit 1 = DMA3 module is disabled 0 = DMA3 module is enabled bit 3-0 Unimplemented: Read as ‘0’ 2009-2011 Microchip Technology Inc. Preliminary DS70616E-page 187 ...
Page 188
... PIC24EPXXXGU810/814 NOTES: DS70616E-page 188 Preliminary 2009-2011 Microchip Technology Inc. ...
Page 189
... WR Port Data Latch Read LAT Read Port 2009-2011 Microchip Technology Inc. the I/O pin. The logic also prevents “loop through,” in which a port’s digital output can drive the input of a peripheral that shares the same pin. illustrates how ports are shared with other peripherals and the associated I/O pin to which they are connected ...
Page 190
... OL EXAMPLE 11-1: MOV 0xFF00, W0 MOV W0, TRISB NOP BTSS PORTB, #13 11-1. Preliminary dsPIC33EPXXXMU806/810/814 and PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> outputs ; Delay 1 cycle ; Next Instruction 2009-2011 Microchip Technology Inc. ...
Page 191
... Microchip Technology Inc. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. ...
Page 192
... T5CKR<6:0> T6CKR<6:0> T7CKR<6:0> T8CKR<6:0> T9CKR<6:0> IC1R<6:0> IC2R<6:0> IC3R<6:0> IC4R<6:0> IC5R<6:0> IC6R<6:0> IC7R<6:0> IC8R<6:0> OCFAR<6:0> OCFBR<6:0> FLT1R<6:0> FLT2R<6:0> FLT3R<6:0> FLT4R<6:0> QEA1R<6:0> QEB1R<6:0> INDX1R<6:0> HOM1R<6:0> QEA2R<6:0> QEB2R<6:0> INDX2R<6:0> HOM2R<6:0> U1RXR<6:0> U1CTSR<6:0> U2RXR<6:0> U2CTSR<6:0> SDI1R<6:0> SCK1R<6:0> SS1R<6:0> SS2R<6:0> CSDIR<6:0> 2009-2011 Microchip Technology Inc. ...
Page 193
... Compensation 7 (2) PWM Synch Input 1 (2) PWM Synch Input 2 Unless otherwise noted, all inputs use the Schmitt input buffers. Note 1: This input source is available on dsPIC33EPXXXMU806/810/814 devices only. 2: 2009-2011 Microchip Technology Inc. Register CSCKIN RPINR24 COFSIN RPINR25 C1RX RPINR26 C2RX RPINR26 ...
Page 194
... I/O RP66 I/O RP67 I/O RP68 I/O RP69 I/O RP70 I/O RP71 I RPI72 I RPI73 I RPI74 I RPI75 I RPI76 I RPI77 I RPI78 I/O RP79 I/O RP80 I RPI81 I/O RP82 I RPI83 I/O RP84 I/O RP85 I RPI86 I/O RP87 I RPI88 I RPI89 2009-2011 Microchip Technology Inc. ...
Page 195
... I/O 110 1100 See Note 1: Section 11.4.3.3 “Virtual Connections” 2009-2011 Microchip Technology Inc. Peripheral Pin Select Pin Assignment Input Register Value Reserved 110 1101 Reserved 110 1110 Reserved 110 1111 Reserved ...
Page 196
... RPn tied to Output Compare 8 output RPn tied to Comparator Output 1 RPn tied to Comparator Output 2 RPn tied to Comparator Output 3 RPn tied to UART3 transmit RPn tied to UART3 ready to send Preliminary MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPnR<5:0> RPn Output Data 48 49 2009-2011 Microchip Technology Inc. ...
Page 197
... QEI2CCMP 110000 REFCLK 110001 This function is available in dsPIC33EPXXXMU806/810/814 devices only. Note 1: 2009-2011 Microchip Technology Inc. Output Name RPn tied to UART4 transmit RPn tied to UART4 ready to send RPn tied to SPI3 data output RPn tied to SPI3 clock output RPn tied to SPI3 slave select ...
Page 198
... While such mappings may be technically possible from a configuration point of view, they may not be supportable from an electrical point of view. Preliminary to the QEI module allows Example 11-1 illustrates how the input Mapping Limitations a small range of fixed peripheral 2009-2011 Microchip Technology Inc. ...
Page 199
... Table 11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to V bit 7-0 Unimplemented: Read as ‘0’ 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 INT1R<6:0> U-0 U-0 U-0 — — — ...
Page 200
... Input tied to CMP1 0000000 = Input tied to V DS70616E-page 200 R/W-0 R/W-0 R/W-0 INT3R<6:0> R/W-0 R/W-0 R/W-0 INT2R<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown 2009-2011 Microchip Technology Inc. ...