DSPIC33FJ128MC706A-E/MR Microchip Technology, DSPIC33FJ128MC706A-E/MR Datasheet - Page 345

16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE

DSPIC33FJ128MC706A-E/MR

Manufacturer Part Number
DSPIC33FJ128MC706A-E/MR
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC706A-E/MR

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug
Pinout I/O Descriptions (table) ............................................ 17
PMD Module
POR and Long Oscillator Start-up Times............................ 86
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
Power-Saving Features .................................................... 155
Program Address Space ..................................................... 37
Program Memory
Q
Quadrature Encoder Interface (QEI) ................................. 193
Quadrature Encoder Interface (QEI) Module
R
Reader Response ............................................................. 349
Registers
 2009 Microchip Technology Inc.
Express ..................................................................... 273
Register Map............................................................... 64
Register Map............................................................... 62
Register Map............................................................... 62
Register Map............................................................... 63
Register Map............................................................... 63
Register Map............................................................... 63
Register Map............................................................... 63
Register Map............................................................... 64
Clock Frequency and Switching................................ 155
Construction................................................................ 70
Data Access from Program Memory Using Program
Data Access from Program Memory Using Table Instruc-
Data Access from, Address Generation...................... 71
Memory Map ............................................................... 37
Table Read High Instructions
Table Read Low Instructions
Visibility Operation ...................................................... 73
Interrupt Vector ........................................................... 38
Organization................................................................ 38
Reset Vector ............................................................... 38
Register Map............................................................... 52
ADxCHS0 (ADCx Input Channel 0 Select) ............... 252
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 251
ADxCON1 (ADCx Control 1)..................................... 246
ADxCON2 (ADCx Control 2)..................................... 248
ADxCON3 (ADCx Control 3)..................................... 249
ADxCON4 (ADCx Control 4)..................................... 250
ADxCSSH (ADCx Input Scan Select High)............... 253
ADxCSSL (ADCx Input Scan Select Low) ................ 253
ADxPCFGH (ADCx Port Configuration High) ........... 254
ADxPCFGL (ADCx Port Configuration Low)............. 254
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 230
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 231
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 231
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 232
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 228
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 229
CiCTRL1 (ECAN Control 1) ...................................... 220
CiCTRL2 (ECAN Control 2) ...................................... 221
Space Visibility.................................................... 73
tions .................................................................... 72
TBLRDH ............................................................. 72
TBLRDL .............................................................. 72
dsPIC33FJXXXMCX06A/X08A/X10A
Preliminary
CiEC (ECAN Transmit/Receive Error Count) ........... 227
CiFCTRL (ECAN FIFO Control) ............................... 223
CiFEN1 (ECAN Acceptance Filter Enable)............... 230
CiFIFO (ECAN FIFO Status) .................................... 224
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) ..... 234
CiFMSKSEL2 (ECAN Filter 15-8 Mask Selection) ... 235
CiINTE (ECAN Interrupt Enable) .............................. 226
CiINTF (ECAN Interrupt Flag) .................................. 225
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
CiRXFnSID (ECAN Acceptance Filter n Standard Identi-
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 237
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 237
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
CiRXMnSID (ECAN Acceptance Filter Mask n Standard
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 238
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 238
CiTRBnDLC (ECAN Buffer n Data Length Control).. 241
CiTRBnDm (ECAN Buffer n Data Field Byte m) ....... 241
CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 240
CiTRBnSID (ECAN Buffer n Standard Identifier)...... 240
CiTRBnSTAT (ECAN Receive Buffer n Status)........ 242
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 239
CiVEC (ECAN Interrupt Code) ................................. 222
CLKDIV (Clock Divisor) ............................................ 150
CORCON (Core Control) ...................................... 30, 92
DFLTxCON (Digital Filter x Control) ......................... 196
DMACS0 (DMA Controller Status 0) ........................ 141
DMACS1 (DMA Controller Status 1) ........................ 143
DMAxCNT (DMA Channel x Transfer Count) ........... 140
DMAxCON (DMA Channel x Control)....................... 137
DMAxPAD (DMA Channel x Peripheral Address) .... 140
DMAxREQ (DMA Channel x IRQ Select) ................. 138
DMAxSTA (DMA Channel x RAM Start Address Offset
DMAxSTB (DMA Channel x RAM Start Address Offset
DSADR (Most Recent DMA RAM Address) ............. 144
I2CxCON (I2Cx Control)........................................... 205
I2CxMSK (I2Cx Slave Mode Address Mask)............ 209
I2CxSTAT (I2Cx Status) ........................................... 207
ICxCON (Input Capture x Control)............................ 174
IEC0 (Interrupt Enable Control 0) ............................. 105
IEC1 (Interrupt Enable Control 1) ............................. 107
IEC2 (Interrupt Enable Control 2) ............................. 109
IEC3 (Interrupt Enable Control 3) ............................. 111
IEC4 (Interrupt Enable Control 4) ............................. 113
IFS0 (Interrupt Flag Status 0) ..................................... 96
IFS1 (Interrupt Flag Status 1) ..................................... 98
IFS2 (Interrupt Flag Status 2) ................................... 100
IFS3 (Interrupt Flag Status 3) ................................... 102
IFS4 (Interrupt Flag Status 4) ................................... 104
INTCON1 (Interrupt Control 1) ................................... 93
INTCON2 (Interrupt Control 2) ................................... 95
INTTREG (Interrupt Control and Status) .................. 132
IPC0 (Interrupt Priority Control 0) ............................. 114
IPC1 (Interrupt Priority Control 1) ............................. 115
IPC10 (Interrupt Priority Control 10) ......................... 124
IPC11 (Interrupt Priority Control 11) ......................... 125
IPC12 (Interrupt Priority Control 12) ......................... 126
IPC13 (Interrupt Priority Control 13) ......................... 127
IPC14 (Interrupt Priority Control 14) ......................... 128
fier) ................................................................... 233
fier) ................................................................... 233
Identifier) .......................................................... 236
Identifier) .......................................................... 236
A) ...................................................................... 139
B) ...................................................................... 139
DS70594B-page 345

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