DSPIC33FJ128MC706A-H/PT Microchip Technology, DSPIC33FJ128MC706A-H/PT Datasheet - Page 146

16 Bit MCU/DSP 40MIPS 128KB FLASH 64 TQFP 10x10x1mm TRAY

DSPIC33FJ128MC706A-H/PT

Manufacturer Part Number
DSPIC33FJ128MC706A-H/PT
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC706A-H/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Oscillator
dsPIC33FJXXXMCX06A/X08A/X10A
9.1
There are seven system clock options provided by the
dsPIC33FJXXXMCX06A/X08A/X10A:
• FRC Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• LPRC Oscillator
• FRC Oscillator with Postscaler
9.1.1
The FRC (Fast RC) internal oscillator runs at a nominal
frequency of 7.37 MHz. The user software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The primary oscillator can use one of the following as
its clock source:
1.
2.
3.
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
The LPRC (Low-Power RC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output
configuration is described in Section 9.1.3 “PLL
Configuration”.
The FRC frequency depends on the FRC accuracy
(see Table 26-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4).
9.1.2
The oscillator source that is used at a device Power-on
Reset event is selected using Configuration bit settings.
The oscillator Configuration bit settings are located in
the Configuration registers in the program memory.
(Refer to Section 23.1 “Configuration Bits” for further
details.) The Initial Oscillator Selection Configuration
bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary
DS70594B-page 146
XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
HS (High-Speed Crystal): Crystals in the range
of 10 MHz to 40 MHz. The crystal is connected
to the OSC1 and OSC2 pins.
EC (External Clock): External clock signal is
directly applied to the OSC1 pin.
frequencies
CPU Clocking System
SYSTEM CLOCK SOURCES
SYSTEM CLOCK SELECTION
Mode
Select
for
device
Configuration
operation.
PLL
bits,
Preliminary
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,
frequency is in the range of 100 MHz to 200 MHz.
POSCMD<1:0> (FOSC<1:0>), select the oscillator
source that is used at a Power-on Reset. The FRC
primary oscillator is the default (unprogrammed)
selection.
The Configuration bits allow users to choose between
twelve different clock modes, shown in Table 9-1.
The output of the oscillator (or the output of the PLL if a
PLL mode has been selected), F
generate the device instruction clock (F
peripheral clock time base (F
operating speed of the device and speeds up to 40 MHz
are supported by the dsPIC33FJXXXMCX06A/X08A/
X10A architecture.
Instruction execution speed or device operating
frequency, F
EQUATION 9-1:
9.1.3
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides a significant amount of
flexibility in selecting the device operating speed. A
block diagram of the PLL is shown in Figure 9-2.
The output of the primary oscillator or FRC, denoted as
‘F
3, ... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected to be in the range of 0.8 MHz to 8 MHz.
Since the minimum prescale factor is 2, this implies that
F
16 MHz. The prescale factor, ‘N1’, is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
The VCO output is further divided by a postscale factor,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
generates device operating speeds of 6.25-40 MIPS.
For a primary oscillator or FRC oscillator output, ‘F
the PLL output, ‘F
equation:
EQUATION 9-2:
IN
IN
OSC
’, is divided down by a prescale factor (N1) of 2,
must be chosen to be in the range of 1.6 MHz to
) is in the range of 12.5 MHz to 80 MHz, which
PLL
PLL CONFIGURATION
CY
feedback divisor,
, is given by the following equation:
F
OSC
OSC
F
=
CY
DEVICE OPERATING
FREQUENCY
F
 2009 Microchip Technology Inc.
OSC
F
’, is given by the following
=
IN
F
-------------
CALCULATION
OSC
2
------------------ -
N1 N2
OSC
P
selected
M
). F
, is divided by 2 to
CY
CY
defines the
using
) and the
the
IN
’,

Related parts for DSPIC33FJ128MC706A-H/PT