DSPIC33FJ128MC706A-H/PT Microchip Technology, DSPIC33FJ128MC706A-H/PT Datasheet - Page 262

16 Bit MCU/DSP 40MIPS 128KB FLASH 64 TQFP 10x10x1mm TRAY

DSPIC33FJ128MC706A-H/PT

Manufacturer Part Number
DSPIC33FJ128MC706A-H/PT
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC706A-H/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
dsPIC33FJXXXMCX06A/X08A/X10A
23.5
dsPIC33FJXXXMCX06A/X08A/X10A devices imple-
ment a JTAG interface, which supports boundary scan
device testing, as well as in-circuit programming.
Detailed information on the interface will be provided in
future revisions of the document.
23.6
The
offer the advanced implementation of CodeGuard™
Security. CodeGuard Security enables multiple parties
to securely share resources (memory, interrupts and
peripherals) on a single chip. This feature helps protect
individual Intellectual Property (IP) in collaborative
system designs.
When coupled with software encryption libraries,
CodeGuard™ Security can be used to securely update
Flash even when multiple IPs are resident on the single
chip. The code protection features vary depending on
the actual device implemented. The following sections
provide an overview of these features.
The code protection features are controlled by the
Configuration registers: FBS, FSS and FGS.
DS70594B-page 262
Note:
dsPIC33FJXXXMCX06A/X08A/X10A
JTAG Interface
Code Protection and
CodeGuard™ Security
Refer to Section 23. “CodeGuard™
Security”
“dsPIC33F/PIC24H
Manual” for further information on usage,
configuration and operation of CodeGuard
Security.
(DS70199)
Family
Reference
in
devices
the
Preliminary
23.7
dsPIC33FJXXXMCX06A/X08A/X10A
signal controllers can be serially programmed while in
the end application circuit. This is simply done with two
lines for clock and data, and three other lines for power,
ground and the programming sequence. This allows
customers to manufacture boards with unprogrammed
devices and then program the digital signal controller
just before shipping the product. This also allows the
most recent firmware, or a custom firmware, to be
programmed. Please refer to the “dsPIC33F Flash
Programming Specification” (DS70152) document for
details about ICSP.
Any one out of three pairs of programming clock/data
pins may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
23.8
When MPLAB
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any one out of three pairs of debugging clock/data pins
may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
In-Circuit Debugger
DD
In-Circuit Serial Programming
, V
®
SS
ICD 2 is selected as a debugger, the
and the PGECx/PGEDx pin pair. In
 2009 Microchip Technology Inc.
family
digital

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