DSPIC33FJ128MC706AT-I/MR Microchip Technology, DSPIC33FJ128MC706AT-I/MR Datasheet - Page 137

16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm T/R

DSPIC33FJ128MC706AT-I/MR

Manufacturer Part Number
DSPIC33FJ128MC706AT-I/MR
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC706AT-I/MR

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.1
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-Bit DMA Channel Control register
• A 16-Bit DMA Channel IRQ Select register
• A 16-Bit DMA RAM Primary Start Address Offset
REGISTER 8-1:
 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-6
bit 5-4
bit 3-2
bit 1-0
(DMAxCON)
(DMAxREQ)
register (DMAxSTA)
R/W-0
CHEN
U-0
DMAC Registers
CHEN: Channel Enable bit
1 = Channel enabled
0 = Channel disabled
SIZE: Data Transfer Size bit
1 = Byte
0 = Word
DIR: Transfer Direction bit (source/destination bus select)
1 = Read from DMA RAM address; write to peripheral address
0 = Read from peripheral address; write to DMA RAM address
HALF: Early Block Transfer Complete Interrupt Select bit
1 = Initiate block transfer complete interrupt when half of the data has been moved
0 = Initiate block transfer complete interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0 = Normal operation
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Operating Mode Select bits
11 = Reserved
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10 = Continuous, Ping-Pong modes enabled
01 = One-Shot, Ping-Pong modes disabled
00 = Continuous, Ping-Pong modes disabled
R/W-0
SIZE
U-0
DMAxCON: DMA CHANNEL x CONTROL REGISTER
dsPIC33FJXXXMCX06A/X08A/X10A
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
DIR
AMODE<1:0>
R/W-0
R/W-0
HALF
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NULLW
R/W-0
• A 16-Bit DMA RAM Secondary Start Address
• A 16-Bit DMA Peripheral Address register
• A 10-Bit DMA Transfer Count register (DMAxCNT)
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
U-0
Offset register (DMAxSTB)
(DMAxPAD)
U-0
U-0
x = Bit is unknown
R/W-0
U-0
MODE<1:0>
DS70594B-page 137
R/W-0
U-0
bit 8
bit 0

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