DSPIC33FJ128MC706T-I/PT Microchip Technology, DSPIC33FJ128MC706T-I/PT Datasheet - Page 9

• Manufacturer Part Number: DSPIC33FJ128MC706T-I/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC706T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
3.1
The dsPIC33F CPU module has a 16-bit (data)
modified Harvard architecture with an enhanced
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word with a variable
length opcode field. The Program Counter (PC) is
23 bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
memory implemented, as illustrated in Figure 3-1,
varies from one device to another. A single-cycle
instruction prefetch mechanism is used to help
maintain
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and
interruptible at any point.
The dsPIC33F devices have sixteen 16-bit working
registers in the programmer’s model. Each of the
working registers can serve as a data, address or
address offset register. The 16th working register
(W15) operates as a software Stack Pointer (SP) for
interrupts and calls.
The dsPIC33F instruction set has two classes of
instructions: the MCU class of instructions and the DSP
class of instructions. These two instruction classes are
seamlessly integrated into a single CPU. The
instruction set includes many addressing modes and is
designed for optimum C compiler efficiency.
3.1.1
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device specific.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data space mapping feature lets any
instruction access program space as if it were data
space.
The data space includes 2 Kbytes of DMA RAM, which
is primarily used for DMA data transfers, but may be
used as general purpose RAM.
© 2005 Microchip Technology Inc.
REPEAT
CPU ARCHITECTURE
Overview
throughput
DATA MEMORY OVERVIEW
instructions,
and
both
provides
of
which
predictable
Preliminary
are
FIGURE 3-1:
Address Error Trap Vector
Reset – GOTO Instruction
Reset – Target Address
Stack Error Trap Vector
Math Error Trap Vector
Alternate Vector Table
Osc. Fail Trap Vector
Interrupt Vector Table
Registers (12 x 8-bit)
Device ID (2 x 16-bit)
Device Configuration
DMA Error Vector
Program Memory
Reserved Vector
Reserved Vector
(87296 x 24-bit)
User Flash
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PROGRAM SPACE
MEMORY MAP
dsPIC33F
DS70155C-page 7
7FFFFE
800000
F7FFFE
F80000
F80016
F80018
FEFFFE
FF0000
FF0002
FF0004
FFFFFE
000000
000002
000004
000014
0000FE
000100
000104
0001FE
000200
02ABFE
02AC00